公开(公告)号：US12300820B2

公开(公告)日：2025-05-13

申请号：US18219951

申请日：2023-07-10

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

Inventor： Teppei Oguni ,  Takeshi Osada ,  Toshihiko Takeuchi ,  Kuniharu Nomoto

IPC: H01M4/587 ,  B82Y30/00 ,  B82Y40/00 ,  C25D5/48 ,  C25D5/50 ,  C25D13/02 ,  C25D13/12 ,  H01M4/04 ,  H01M4/133 ,  H01M4/1393 ,  H01M4/66 ,  H01M4/70

Abstract: Graphene is formed with a practically uniform thickness on an uneven object. The object is immersed in a graphene oxide solution, and then taken out of the solution and dried; alternatively, the object and an electrode are immersed therein and voltage is applied between the electrode and the object used as an anode. Graphene oxide is negatively charged, and thus is drawn to and deposited on a surface of the object, with a practically uniform thickness. After that, the object is heated in vacuum or a reducing atmosphere, so that the graphene oxide is reduced to be graphene. In this manner, a graphene layer with a practically uniform thickness can be formed even on a surface of the uneven object.

公开(公告)号：US11784259B2

公开(公告)日：2023-10-10

申请号：US17697152

申请日：2022-03-17

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shunpei Yamazaki ,  Hiromi Sawai ,  Ryo Tokumaru ,  Toshihiko Takeuchi ,  Tsutomu Murakawa ,  Sho Nagamatsu ,  Tomoaki Moriwaka

IPC: H01L29/00 ,  H01L27/00 ,  H01L29/786 ,  H01L29/04 ,  H01L29/06 ,  H01L29/66 ,  H10B12/00

CPC classification number: H01L29/7869 ,  H01L29/04 ,  H01L29/0665 ,  H01L29/66742 ,  H10B12/05 ,  H10B12/315

Abstract: A semiconductor device having favorable electrical characteristics is provided. The semiconductor device includes a conductor, a first insulator in contact with a side surface of the conductor, a second insulator in contact with a top surface of the conductor and a top surface of the first insulator, and an oxide over the second insulator. The oxide includes a region that overlaps with the conductor with the second insulator interposed therebetween. The maximum height of a roughness curve (Rz) of the top surface of the conductor is 6.0 nm or smaller. The region includes crystals, and c-axes of the crystals are aligned in the normal direction of the top surface of the conductor.

公开(公告)号：US11495691B2

公开(公告)日：2022-11-08

申请号：US17056072

申请日：2019-05-27

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Toshihiko Takeuchi ,  Naoto Yamade ,  Yutaka Okazaki ,  Sachiaki Tezuka ,  Shunpei Yamazaki

IPC: H01L29/78 ,  H01L29/786 ,  H01L21/8234 ,  H01L27/06 ,  H01L27/088 ,  H01L27/108 ,  H01L27/12 ,  H01L29/792

Abstract: The semiconductor device includes a first conductor and a second conductor; a first insulator to a third insulator; and a first oxide to a third oxide. The first conductor is disposed to be exposed from a top surface of the first insulator. The first oxide is disposed over the first insulator and the first conductor. A first opening reaching the first conductor is provided in the first oxide. The second oxide is disposed over the first oxide. The second oxide comprises a first region, a second region, and a third region positioned between the first region and the second region. The third oxide is disposed over the second oxide. The second insulator is disposed over the third oxide. The second conductor is disposed over the second insulator. The third insulator is disposed to cover the first region and the second region and to be in contact with the top surface of the first insulator.

公开(公告)号：US11282964B2

公开(公告)日：2022-03-22

申请号：US16760050

申请日：2018-11-26

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shunpei Yamazaki ,  Hiromi Sawai ,  Ryo Tokumaru ,  Toshihiko Takeuchi ,  Tsutomu Murakawa ,  Sho Nagamatsu ,  Tomoaki Moriwaka

IPC: H01L27/00 ,  H01L29/00 ,  H01L29/786 ,  H01L27/108 ,  H01L29/04 ,  H01L29/06 ,  H01L29/66

Abstract: A semiconductor device having favorable electrical characteristics is provided. The semiconductor device includes a conductor, a first insulator in contact with a side surface of the conductor, a second insulator in contact with a top surface of the conductor and a top surface of the first insulator, and an oxide over the second insulator. The oxide includes a region that overlaps with the conductor with the second insulator interposed therebetween. The maximum height of a roughness curve (Rz) of the top surface of the conductor is 6.0 nm or smaller. The region includes crystals, and c-axes of the crystals are aligned in the normal direction of the top surface of the conductor.

公开(公告)号：US11177176B2

公开(公告)日：2021-11-16

申请号：US16649890

申请日：2018-10-09

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shunpei Yamazaki ,  Toshihiko Takeuchi ,  Hiromi Sawai ,  Ryota Hodo ,  Katsuaki Tochibayashi

IPC: H01L21/8234 ,  H01L29/786

Abstract: A semiconductor device that can have favorable electrical characteristics and can be highly integrated is provided.
The semiconductor device includes a first insulator; a second insulator over the first insulator; an oxide over the second insulator; a first conductor and a second conductor over the oxide; a third insulator over the oxide; a third conductor positioned over the third insulator and overlapping with the oxide; a fourth insulator in contact with the second insulator, a side surface of the oxide, a side surface of the first conductor, a top surface of the first conductor, a side surface of the second conductor, a top surface of the second conductor, and a side surface of the third insulator; and a fifth insulator in contact with a top surface of the third insulator and a top surface of the third conductor, and a top surface of the fourth insulator is in contact with the fifth insulator.

公开(公告)号：US10559667B2

公开(公告)日：2020-02-11

申请号：US14830817

申请日：2015-08-20

Applicant: Semiconductor Energy Laboratory Co., LTD.

Inventor： Masashi Tsubuku ,  Shunpei Yamazaki ,  Hidetomo Kobayashi ,  Kazuaki Ohshima ,  Masashi Fujita ,  Toshihiko Takeuchi

IPC: H01L29/24 ,  H01L29/786 ,  H01L27/12 ,  H01L27/06

Abstract: A semiconductor device in which a transistor has the characteristic of low off-state current is provided. The transistor comprises an oxide semiconductor layer having a channel region whose channel width is smaller than 70 nm. A temporal change in off-state current of the transistor over time can be represented by Formula (a2). In Formula (a2), IOFF represents the off-state current, t represents time during which the transistor is off, α and τ are constants, β is a constant that satisfies 0

公开(公告)号：US10544041B2

公开(公告)日：2020-01-28

申请号：US15810953

申请日：2017-11-13

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

Inventor： Teppei Oguni ,  Takeshi Osada ,  Toshihiko Takeuchi

IPC: B82Y30/00 ,  C25D13/22 ,  H01M4/04 ,  H01M4/13 ,  H01M4/133 ,  H01M4/134 ,  H01M4/139 ,  H01M4/1393 ,  H01M4/1395 ,  H01M4/36 ,  H01M4/587 ,  H01M10/0525 ,  C25D13/02 ,  H01M4/02

Abstract: To form graphene to a practically even thickness on an object having an uneven surface or a complex surface, in particular, an object having a surface with a three-dimensional structure due to complex unevenness, or an object having a curved surface. The object and an electrode are immersed in a graphene oxide solution, and voltage is applied between the object and the electrode. At this time, the object serves as an anode. Graphene oxide is attracted to the anode because of being negatively charged, and deposited on the surface of the object to have a practically even thickness. A portion where graphene oxide is deposited is unlikely coated with another graphene oxide. Thus, deposited graphene oxide is reduced to graphene, whereby graphene can be formed to have a practically even thickness on an object having surface with complex unevenness.

公开(公告)号：US10074733B2

公开(公告)日：2018-09-11

申请号：US15605160

申请日：2017-05-25

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Tetsuhiro Tanaka ,  Toshihiko Takeuchi ,  Yasumasa Yamane ,  Takayuki Inoue ,  Shunpei Yamazaki

IPC: H01L29/66 ,  H01L29/786 ,  H01L29/49

CPC classification number: H01L29/66969 ,  H01L29/4908 ,  H01L29/7869 ,  H01L29/78696

Abstract: A manufacturing method of a semiconductor device in which the threshold voltage is adjusted is provided. The semiconductor device includes a first semiconductor, an electrode electrically connected to the first semiconductor, a gate electrode, and an electron trap layer between the gate electrode and the first semiconductor. By performing heat treatment at higher than or equal to 125° C. and lower than or equal to 450° C. and, at the same time, keeping a potential of the gate electrode higher than a potential of the electrode for 1 second or more, the threshold voltage is increased.

公开(公告)号：US09817040B2

公开(公告)日：2017-11-14

申请号：US14625984

申请日：2015-02-19

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

Inventor： Masashi Tsubuku ,  Kazuma Furutani ,  Atsushi Hirose ,  Toshihiko Takeuchi

IPC: G01R31/26 ,  G01R19/00

CPC classification number: G01R19/0092

Abstract: A minute current measurement method is provided. In the current measurement method, a first potential is applied to a first terminal of a transistor under test, a second potential is applied to a first terminal of a first transistor, the first transistor is turned on to accumulate a predetermined charge in a node electrically connecting a second terminal of the transistor under test with a second terminal of the first transistor, a third potential of an output terminal of a read circuit electrically connected to the node is measured, the first transistor is turned off, a fourth potential of the output terminal of the read circuit electrically connected to the node is measured, the amount of the charge held by the node is estimated from the amount of change in the potential of the output terminal of the read circuit (e.g., a difference between the third potential and the fourth potential), and a value of current flowing between the first terminal of the transistor under test and the second terminal of the first transistor is calculated from the amount of the charge held by the node.

公开(公告)号：US09166021B2

公开(公告)日：2015-10-20

申请号：US14047639

申请日：2013-10-07

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Sachiaki Tezuka ,  Tetsuhiro Tanaka ,  Toshihiko Takeuchi ,  Hideomi Suzawa ,  Suguru Hondo

IPC: H01L21/00 ,  H01L21/16 ,  H01L29/66 ,  H01L21/28 ,  H01L21/8234 ,  H01L29/78 ,  H01L29/49 ,  H01L21/8238 ,  H01L29/786

CPC classification number: H01L29/7869 ,  H01L21/28185 ,  H01L21/28194 ,  H01L21/823462 ,  H01L21/823857 ,  H01L29/1054 ,  H01L29/42384 ,  H01L29/4908 ,  H01L29/66765 ,  H01L29/66969 ,  H01L29/78

Abstract: Stable electrical characteristics and high reliability are provided for a miniaturized semiconductor device including an oxide semiconductor, and the semiconductor device is manufactured. The semiconductor device includes a base insulating layer; an oxide stack which is over the base insulating layer and includes an oxide semiconductor layer; a source electrode layer and a drain electrode layer over the oxide stack; a gate insulating layer over the oxide stack, the source electrode layer, and the drain electrode layer; a gate electrode layer over the gate insulating layer; and an interlayer insulating layer over the gate electrode layer. In the semiconductor device, the defect density in the oxide semiconductor layer is reduced.

Abstract translation: 为包括氧化物半导体的小型半导体器件提供稳定的电特性和高可靠性，并且制造半导体器件。 半导体器件包括基极绝缘层; 氧化物堆叠，其在所述基底绝缘层上方并且包括氧化物半导体层; 氧化层上的源电极层和漏电极层; 氧化层上的栅极绝缘层，源电极层和漏电极层; 栅绝缘层上的栅电极层; 以及在栅电极层上的层间绝缘层。 在半导体器件中，氧化物半导体层中的缺陷密度降低。