公开(公告)号：US09748401B2

公开(公告)日：2017-08-29

申请号：US14547285

申请日：2014-11-19

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Masashi Tsubuku ,  Takayuki Inoue ,  Suzunosuke Hiraishi ,  Erumu Kikuchi ,  Hiromichi Godo ,  Shuhei Yoshitomi ,  Koki Inoue ,  Akiharu Miyanaga ,  Shunpei Yamazaki

IPC: H01L29/786 ,  H01L29/40

CPC classification number: H01L29/7869 ,  H01L29/408

Abstract: Manufactured is a transistor including an oxide semiconductor layer, a source electrode layer and a drain electrode layer overlapping with part of the oxide semiconductor layer, a gate insulating layer overlapping with the oxide semiconductor layer, the source electrode layer, and the drain electrode layer, and a gate electrode overlapping with part of the oxide semiconductor layer with the gate insulating layer provided therebetween, wherein, after the oxide semiconductor layer which is to be a channel formation region is irradiated with light and the light irradiation is stopped, a relaxation time of carriers in photoresponse characteristics of the oxide semiconductor layer has at least two kinds of modes: τ1 and τ2, τ1

公开(公告)号：US09666697B2

公开(公告)日：2017-05-30

申请号：US14313145

申请日：2014-06-24

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Tetsuhiro Tanaka ,  Toshihiko Takeuchi ,  Yasumasa Yamane ,  Takayuki Inoue ,  Shunpei Yamazaki

IPC: H01L29/49 ,  H01L29/786 ,  H01L29/66

CPC classification number: H01L29/66969 ,  H01L29/4908 ,  H01L29/7869 ,  H01L29/78696

Abstract: A manufacturing method of a semiconductor device in which the threshold voltage is adjusted is provided. The semiconductor device includes a first semiconductor, an electrode electrically connected to the first semiconductor, a gate electrode, and an electron trap layer between the gate electrode and the first semiconductor. By performing heat treatment at higher than or equal to 125° C. and lower than or equal to 450° C. and, at the same time, keeping a potential of the gate electrode higher than a potential of the electrode for 1 second or more, the threshold voltage is increased.

公开(公告)号：US09601633B2

公开(公告)日：2017-03-21

申请号：US14330113

申请日：2014-07-14

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Takayuki Inoue ,  Masashi Tsubuku ,  Suzunosuke Hiraishi ,  Junichiro Sakata ,  Erumu Kikuchi ,  Hiromichi Godo ,  Akiharu Miyanaga ,  Shunpei Yamazaki

IPC: H01L29/10 ,  H01L29/12 ,  H01L29/786 ,  H01L29/417 ,  H01L29/24 ,  H01L31/032 ,  H01L31/18 ,  H01L27/12

CPC classification number: H01L29/7869 ,  H01L27/1225 ,  H01L29/24 ,  H01L29/41733 ,  H01L31/032 ,  H01L31/18

Abstract: An oxide semiconductor layer in which “safe” traps exist exhibits two kinds of modes in photoresponse characteristics. By using the oxide semiconductor layer, a transistor in which light deterioration is suppressed to the minimum and the electric characteristics are stable can be achieved. The oxide semiconductor layer exhibiting two kinds of modes in photoresponse characteristics has a photoelectric current value of 1 pA to 10 nA inclusive. When the average time τ1 until which carriers are captured by the “safe” traps is large enough, there are two kinds of modes in photoresponse characteristics, that is, a region where the current value falls rapidly and a region where the current value falls gradually, in the result of a change in photoelectric current over time.

公开(公告)号：US09449853B2

公开(公告)日：2016-09-20

申请号：US14471766

申请日：2014-08-28

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Yoshitaka Yamamoto ,  Tetsuhiro Tanaka ,  Takayuki Inoue ,  Hideomi Suzawa

IPC: H01L21/336 ,  H01L21/441 ,  H01L21/473 ,  H01L29/786 ,  H01L29/51 ,  H01L21/02 ,  H01L29/66 ,  H01L29/423 ,  H01L21/28 ,  H01L29/792 ,  H01L21/311 ,  H01L21/3213 ,  H01L21/465 ,  H01L29/49 ,  H01L27/12 ,  H01L21/316

CPC classification number: H01L29/7869 ,  H01L21/0214 ,  H01L21/02181 ,  H01L21/02266 ,  H01L21/02274 ,  H01L21/28194 ,  H01L21/28282 ,  H01L21/31116 ,  H01L21/31122 ,  H01L21/31645 ,  H01L21/32136 ,  H01L21/441 ,  H01L21/465 ,  H01L21/473 ,  H01L27/1225 ,  H01L29/24 ,  H01L29/42384 ,  H01L29/4908 ,  H01L29/517 ,  H01L29/66969 ,  H01L29/78648 ,  H01L29/78693 ,  H01L29/78696 ,  H01L29/792

Abstract: A semiconductor device in which the threshold is adjusted is provided. In a transistor including a semiconductor, a source or drain electrode electrically connected to the semiconductor, a gate electrode, and an electron trap layer between the gate electrode and the semiconductor, the electron trap layer includes crystallized hafnium oxide. The crystallized hafnium oxide is deposited by a sputtering method using hafnium oxide as a target. When the substrate temperature is Tsub (° C.) and the proportion of oxygen in an atmosphere is P (%) in the sputtering method, P≧45−0.15×Tsub is satisfied. The crystallized hafnium oxide has excellent electron trapping properties. By the trap of an appropriate number of electrons, the threshold of the semiconductor device can be adjusted.

Abstract translation: 提供其中调整阈值的半导体器件。 在包括半导体，与半导体电连接的源电极或漏电极，栅电极和栅电极和半导体之间的电子捕获层的晶体管中，电子捕获层包括结晶的氧化铪。 通过使用氧化铪作为靶的溅射法沉积结晶的氧化铪。 溅射法中，衬底温度为Tsub（℃），气氛中氧的比例为P（％）时，P≥45〜0.15×Tsub。 结晶的氧化铪具有优异的电子捕获性能。 通过适当数量的电子的陷阱，可以调整半导体器件的阈值。

公开(公告)号：US09443990B2

公开(公告)日：2016-09-13

申请号：US14464966

申请日：2014-08-21

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Kiyoshi Kato ,  Yasuhiko Takemura ,  Tetsuhiro Tanaka ,  Takayuki Inoue ,  Toshihiko Takeuchi ,  Yasumasa Yamane ,  Shunpei Yamazaki

IPC: H03K19/003 ,  H01L21/324 ,  H01L29/792 ,  H01L21/28 ,  H01L29/423 ,  H01L29/66 ,  G11C16/04 ,  H01L27/12 ,  H03K19/00 ,  H03K19/177

CPC classification number: H01L29/792 ,  G11C16/0466 ,  H01L21/28282 ,  H01L27/1225 ,  H01L29/4234 ,  H01L29/66833 ,  H03K19/0013 ,  H03K19/17736

Abstract: A manufacturing method of a semiconductor device in which the threshold is adjusted is provided. In a semiconductor device including a plurality of transistors arranged in a matrix each including a semiconductor, a source or drain electrode electrically connected to the semiconductor, a gate electrode, and a charge trap layer between the gate electrode and the semiconductor, electrons are trapped in the charge trap layer by performing heat treatment and, simultaneously, keeping a potential of the gate electrode higher than that of the source or drain electrode for 1 second or more. By this process, the threshold increases and Icut decreases. A circuit that supplies a signal to the gate electrode (e.g., word line driver) is provided with a selection circuit formed of an OR gate, an XOR gate, or the like, whereby potentials of word lines can be simultaneously set higher than potentials of bit lines.

Abstract translation: 提供了其中调整阈值的半导体器件的制造方法。 在包括以矩阵形式排列的多个晶体管的半导体器件中，每个晶体管包括半导体，与该半导体电连接的源极或漏极，栅电极和栅电极与半导体之间的电荷陷阱层，电子被俘获在 通过进行热处理，同时使栅电极的电位比源极或漏极的电位高1秒以上。 通过该过程，阈值增加并且Icut减小。 向门电极（例如字线驱动器）提供信号的电路设置有由或门，异或门等形成的选择电路，由此可以将字线的电位同时设置为高于电位 位线。

公开(公告)号：US09117919B2

公开(公告)日：2015-08-25

申请号：US14278634

申请日：2014-05-15

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shunpei Yamazaki ,  Yusuke Nonaka ,  Takayuki Inoue ,  Masashi Tsubuku ,  Kengo Akimoto ,  Akiharu Miyanaga

IPC: H01L29/12 ,  H01L29/04 ,  H01L31/036 ,  H01L31/0376 ,  H01L31/20 ,  H01L27/01 ,  H01L27/12 ,  H01L31/0392 ,  H01L29/786

CPC classification number: H01L29/7869 ,  H01L21/02488 ,  H01L21/02554 ,  H01L21/02565 ,  H01L29/04 ,  H01L29/24 ,  H01L29/78603

Abstract: An object is to provide a semiconductor device including an oxide semiconductor film, which has stable electrical characteristics and high reliability. A stack of first and second material films is formed by forming the first material film (a film having a hexagonal crystal structure) having a thickness of 1 nm to 10 nm over an insulating surface and forming the second material film having a hexagonal crystal structure (a crystalline oxide semiconductor film) using the first material film as a nucleus. As the first material film, a material film having a wurtzite crystal structure (e.g., gallium nitride or aluminum nitride) or a material film having a corundum crystal structure (α-Al2O3, α-Ga2O3, In2O3, Ti2O3, V2O3, Cr2O3, or α-Fe2O3) is used.

Abstract translation: 本发明的目的是提供一种具有稳定的电气特性和高可靠性的氧化物半导体膜的半导体装置。 通过在绝缘表面上形成厚度为1nm至10nm的第一材料膜（具有六方晶体结构的膜）形成第一和第二材料膜的叠层，并形成具有六方晶系结构的第二材料膜（ 使用第一材料膜作为核的结晶氧化物半导体膜）。 作为第一材料膜，具有纤锌矿晶体结构的材料膜（例如氮化镓或氮化铝）或具有刚玉晶体结构的材料膜（α-Al 2 O 3，α-Ga 2 O 3，In 2 O 3，Ti 2 O 3，V 2 O 3，Cr 2 O 3，或 α-Fe 2 O 3）。

公开(公告)号：US08643182B2

公开(公告)日：2014-02-04

申请号：US13908047

申请日：2013-06-03

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Tomokazu Yokoi ,  Takayuki Inoue ,  Makoto Furuno

IPC: H01L23/12

CPC classification number: H01L29/12 ,  H01M4/0428 ,  H01M4/134 ,  H01M4/366 ,  H01M4/386

Abstract: Provided are a semiconductor film including silicon microstructures formed at high density, and a manufacturing method thereof. Further, provided are a semiconductor film including silicon microstructures whose density is controlled, and a manufacturing method thereof. Furthermore, a power storage device with improved charge-discharge capacity is provided. A manufacturing method in which a semiconductor film with a silicon layer including silicon structures is formed over a substrate with a metal surface is used. The thickness of a silicide layer formed by reaction between the metal and the silicon is controlled, so that the grain sizes of silicide grains formed at an interface between the silicide layer and the silicon layer are controlled and the shapes of the silicon structures are controlled. Such a semiconductor film can be applied to an electrode of a power storage device.

Abstract translation: 提供了包括以高密度形成的硅微结构的半导体膜及其制造方法。 此外，提供了包括其密度被控制的硅微结构的半导体膜及其制造方法。 此外，提供了具有改善的充放电容量的蓄电装置。 使用其中在具有金属表面的基板上形成具有包括硅结构的硅层的半导体膜的制造方法。 控制由金属与硅之间的反应形成的硅化物层的厚度，从而控制在硅化物层和硅层之间的界面处形成的硅化物晶粒的晶粒尺寸，并且控制硅结构的形状。 这样的半导体膜可以应用于蓄电装置的电极。

公开(公告)号：US10586869B2

公开(公告)日：2020-03-10

申请号：US14803483

申请日：2015-07-20

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shunpei Yamazaki ,  Yusuke Nonaka ,  Takayuki Inoue ,  Masashi Tsubuku ,  Kengo Akimoto ,  Akiharu Miyanaga

IPC: H01L29/786 ,  H01L29/04 ,  H01L23/552 ,  H01L23/00 ,  H01L29/66

Abstract: An object is to manufacture a semiconductor device including an oxide semiconductor film, which has stable electric characteristics and high reliability. A crystalline oxide semiconductor film is formed, without performing a plurality of steps, as follows: by utilizing a difference in atomic weight of plural kinds of atoms included in an oxide semiconductor target, zinc with low atomic weight is preferentially deposited on an oxide insulating film to form a seed crystal including zinc; and tin, indium, or the like with high atomic weight is deposited on the seed crystal while causing crystal growth. Further, a crystalline oxide semiconductor film is formed by causing crystal growth using a seed crystal with a hexagonal crystal structure including zinc as a nucleus, whereby a single crystal oxide semiconductor film or a substantially single crystal oxide semiconductor film is formed.

公开(公告)号：US10074733B2

公开(公告)日：2018-09-11

申请号：US15605160

申请日：2017-05-25

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Tetsuhiro Tanaka ,  Toshihiko Takeuchi ,  Yasumasa Yamane ,  Takayuki Inoue ,  Shunpei Yamazaki

IPC: H01L29/66 ,  H01L29/786 ,  H01L29/49

CPC classification number: H01L29/66969 ,  H01L29/4908 ,  H01L29/7869 ,  H01L29/78696

Abstract: A manufacturing method of a semiconductor device in which the threshold voltage is adjusted is provided. The semiconductor device includes a first semiconductor, an electrode electrically connected to the first semiconductor, a gate electrode, and an electron trap layer between the gate electrode and the first semiconductor. By performing heat treatment at higher than or equal to 125° C. and lower than or equal to 450° C. and, at the same time, keeping a potential of the gate electrode higher than a potential of the electrode for 1 second or more, the threshold voltage is increased.

公开(公告)号：US09312349B2

公开(公告)日：2016-04-12

申请号：US14322555

申请日：2014-07-02

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

Inventor： Tetsuhiro Tanaka ,  Takayuki Inoue ,  Yoshitaka Yamamoto ,  Hideomi Suzawa ,  Tamae Moriwaka

IPC: H01L21/00 ,  H01L29/423 ,  H01L29/49 ,  H01L29/786

CPC classification number: H01L29/4234 ,  H01L29/4908 ,  H01L29/7869 ,  H01L29/78696

Abstract: To provide a semiconductor device in which the threshold value is controlled. Furthermore, to provide a semiconductor device in which a deterioration in electrical characteristics which becomes more noticeable as a transistor is miniaturized can be suppressed. The semiconductor device includes a first semiconductor film, a source electrode and a drain electrode electrically connected to the first semiconductor film, a gate insulating film, and a gate electrode in contact with the gate insulating film. The gate insulating film includes a first insulating film and a trap film, and charge is trapped in a charge trap state in an interface between the first insulating film and the trap film or inside the trap film.

Abstract translation: 提供其中控制阈值的半导体器件。 此外，为了提供一种半导体器件，其中可以抑制作为晶体管变得更显着的电特性的劣化小型化。 半导体器件包括与栅极绝缘膜接触的第一半导体膜，与第一半导体膜电连接的栅极绝缘膜和栅电极的源电极和漏电极。 栅极绝缘膜包括第一绝缘膜和陷阱膜，并且在第一绝缘膜和陷阱膜之间的界面内或捕获膜内部的电荷陷阱状态下捕获电荷。