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    Semiconductor device, system, and method for operating system
    11.
    发明授权
    Semiconductor device, system, and method for operating system 有权

    公开(公告)号：US10290253B2

    公开(公告)日：2019-05-14

    申请号：US15615997

    申请日：2017-06-07

    Applicant: Semiconductor Energy Laboratory Co., Ltd.

    Inventor： Tatsunori Inoue ,  Takeshi Aoki

    IPC: G09G3/20 ,  G09G3/3225 ,  G09G3/36 ,  H01L27/12 ,  H03K19/08

    Abstract: An object is to provide a semiconductor device that automatically adjusts the luminance of a display device. The semiconductor device includes an illuminometer, a threshold detector, a timing controller, a digital-to-analog converter circuit, a first display panel, and a second display panel. The illuminance of external light is measured with the illuminometer, and the threshold value of digital video data is determined by the threshold detector in accordance with the illuminance. The timing controller generates a signal for the first display panel or a signal for the second display panel on the basis of the threshold value and video data transmitted from the outside. The signal for the first display panel and the signal for the second display panel are input to one digital-to-analog converter circuit and converted into digital signals, and the obtained digital signals are input to a corresponding one of the first display panel and the second display panel.

    Semiconductor device having Schmitt trigger NAND circuit and Schmitt trigger inverter
    15.
    发明授权
    Semiconductor device having Schmitt trigger NAND circuit and Schmitt trigger inverter 有权
    具有施密特触发器NAND电路和施密特触发器的半导体器件

    公开(公告)号：US09245589B2

    公开(公告)日：2016-01-26

    申请号：US14217793

    申请日：2014-03-18

    Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

    Inventor： Takeshi Aoki ,  Yoshiyuki Kurokawa ,  Munehiro Kozuma

    IPC: G11C5/06 ,  G11C7/10

    CPC classification number: G11C5/06 ,  G11C7/1051 ,  G11C7/1057 ,  G11C11/24 ,  G11C14/0054

    Abstract: A nonvolatile semiconductor device which can be driven at low voltage is provided. A nonvolatile semiconductor device with low power consumption is provided. A Schmitt trigger NAND circuit and a Schmitt trigger inverter are included. Data is held in a period when the supply of power supply voltage is continued, and a potential corresponding to the data is stored at a node electrically connected to a capacitor before a period when the supply of power supply voltage is stopped. By utilizing a change in channel resistance of a transistor whose gate is connected to the node, the data is restored in response to the restart of the supply of power supply voltage.

    Abstract translation: 提供了可以以低电压驱动的非易失性半导体器件。 提供了具有低功耗的非易失性半导体器件。 包括施密特触发器NAND电路和施密特触发器反相器。 数据保持在电源电压继续供给的期间，与电源相对应的电位存储在与电容器电连接的节点上，在供给电源电压停止的期间。 通过利用其栅极连接到节点的晶体管的沟道电阻的变化，响应于电源电压的重新启动恢复数据。

    Programmable logic device
    16.
    发明授权
    Programmable logic device 有权
    可编程逻辑器件

    公开(公告)号：US09065438B2

    公开(公告)日：2015-06-23

    申请号：US14305434

    申请日：2014-06-16

    Applicant: Semiconductor Energy Laboratory Co., Ltd.

    Inventor： Takeshi Aoki ,  Yoshiyuki Kurokawa ,  Munehiro Kozuma ,  Takashi Nakagawa

    IPC: H03K19/0185 ,  H03K19/00

    CPC classification number: H03K19/0013 ,  H03K19/018585

    Abstract: Data of a register in a programmable logic element is retained. A volatile storage circuit and a nonvolatile storage circuit are provided in a register of a programmable logic element whose function can be changed in response to a plurality of context signals. The nonvolatile storage circuit includes nonvolatile storage portions for storing data in the register. The number of nonvolatile storage portions corresponds to the number of context signals. With such a structure, the function can be changed each time context signals are switched and data in the register that is changed when the function is changed can be backed up to the nonvolatile storage portion in each function. In addition, the function can be changed each time context signals are switched and the data in the register that is backed up when the function is changed can be recovered to the volatile storage circuit.

    Abstract translation: 可编程逻辑元件中寄存器的数据被保留。 易失性存储电路和非易失性存储电路设置在可编程逻辑元件的寄存器中，该可编程逻辑元件的功能可以响应于多个上下文信号而改变。 非易失性存储电路包括用于将数据存储在寄存器中的非易失性存储部分。 非易失性存储部分的数量对应于上下文信号的数量。 通过这样的结构，可以在每次上下文信号切换时改变功能，并且在功能改变时改变的寄存器中的数据可以备份到每个功能中的非易失性存储部分。 此外，每当上下文信号被切换并且功能改变时备份的寄存器中的数据可以被恢复到易失性存储电路时，可以改变该功能。

    Semiconductor device and driving method thereof
    17.
    发明授权
    Semiconductor device and driving method thereof 有权
    半导体装置及其驱动方法

    公开(公告)号：US09064574B2

    公开(公告)日：2015-06-23

    申请号：US14064264

    申请日：2013-10-28

    Applicant: Semiconductor Energy Laboratory Co., Ltd.

    Inventor： Takeshi Aoki ,  Takayuki Ikeda ,  Yoshiyuki Kurokawa

    IPC: G11C7/08 ,  G11C14/00

    CPC classification number: G11C14/0072

    Abstract: To provide a semiconductor device in which power consumption can be reduced and operation delay due to a stop and a restart of supply of power supply voltage can be suppressed and a driving method thereof. A potential corresponding to data held in a period during which power supply voltage is continuously supplied is saved to a node connected to a capacitor before the supply of power supply voltage is stopped. By utilizing change of channel resistance of a transistor whose gate is the node, data is loaded when the supply of power supply voltage is restarted.

    Abstract translation: 提供一种半导体装置，其能够降低功率消耗，并且可以抑制由于电源电压的停止和重新开始引起的操作延迟及其驱动方法。 在供给电源电压停止之前，与在电源电压连续供给的期间保持的数据对应的电位被保存到与电容器连接的节点。 通过利用栅极为节点的晶体管的沟道电阻的变化，在重新开始供电电源时加载数据。

    SEMICONDUCTOR DEVICE
    18.
    发明申请
    SEMICONDUCTOR DEVICE 有权
    半导体器件

    公开(公告)号：US20150060978A1

    公开(公告)日：2015-03-05

    申请号：US14471151

    申请日：2014-08-28

    Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

    Inventor： Takeshi Aoki

    IPC: H01L27/108 ,  H01L29/12 ,  H01L23/48

    CPC classification number: H01L27/1052 ,  H01L27/108 ,  H01L27/10873 ,  H01L27/1156 ,  H01L27/1225 ,  H01L27/124 ,  H01L27/1255 ,  H01L29/24 ,  H01L29/7869 ,  H01L2924/0002 ,  H01L2924/00012

    Abstract: To provide a semiconductor memory device which can be manufactured with high yield and which can achieve higher integration. A pair of memory cells adjacent to each other in the bit line direction is connected to a bit line through a common contact hole. The pair of memory cells adjacent to each other in the bit line direction shares an electrode connected to the bit line. An oxide semiconductor layer included in the memory cell is provided to overlap with a word line and a capacitor line. A transistor and a capacitor included in the memory cell are each provided to overlap with the bit line connected to the memory cell.

    Abstract translation: 提供可以以高产率制造并可实现更高集成度的半导体存储器件。 在位线方向上彼此相邻的一对存储单元通过公共接触孔连接到位线。 在位线方向上彼此相邻的一对存储单元共享连接到位线的电极。 包括在存储单元中的氧化物半导体层被设置为与字线和电容器线重叠。 包括在存储单元中的晶体管和电容器分别设置为与连接到存储单元的位线重叠。

    Programmable logic device and semiconductor device
    19.
    发明授权
    Programmable logic device and semiconductor device 有权
    可编程逻辑器件和半导体器件

    公开(公告)号：US08952723B2

    公开(公告)日：2015-02-10

    申请号：US14166936

    申请日：2014-01-29

    Applicant: Semiconductor Energy Laboratory Co., Ltd.

    Inventor： Takeshi Aoki ,  Takayuki Ikeda ,  Yoshiyuki Kurokawa ,  Munehiro Kozuma

    IPC: H03K19/094 ,  H01L25/00 ,  H03K19/0175

    CPC classification number: H03K19/1776 ,  H03K19/017581

    Abstract: To provide a PLD having a reduced circuit area and an increased operation speed. In the circuit structure, a gate of a transistor provided between an input terminal and an output terminal of a programmable switch element is in an electrically floating state in a period when a signal is input to the programmable switch element. The structure enables the voltage of a gate to be increased by a boosting effect in response to a signal supplied from programmable logic elements, suppressing a reduction in amplitude voltage. This can reduce a circuit area by a region occupied by a booster circuit such as a pull-up circuit and increase operation speed.

    Abstract translation: 提供具有减小的电路面积和增加的操作速度的PLD。 在电路结构中，设置在可编程开关元件的输入端子和输出端子之间的晶体管的栅极在信号被输入到可编程开关元件的时段内处于电浮动状态。 该结构使得能够响应于从可编程逻辑元件提供的信号的升压效应来增加栅极的电压，从而抑制幅度电压的降低。 这可以通过诸如上拉电路的升压电路占据的区域来减小电路面积，并且增加操作速度。

    PROGRAMMABLE LOGIC DEVICE AND SEMICONDUCTOR DEVICE
    20.
    发明申请
    PROGRAMMABLE LOGIC DEVICE AND SEMICONDUCTOR DEVICE 有权
    可编程逻辑器件和半导体器件

    公开(公告)号：US20140225641A1

    公开(公告)日：2014-08-14

    申请号：US14170825

    申请日：2014-02-03

    Applicant: Semiconductor Energy Laboratory Co., Ltd.

    Inventor： Munehiro Kozuma ,  Yoshiyuki Kurokawa ,  Takayuki Ikeda ,  Takeshi Aoki

    IPC: H03K19/177

    CPC classification number: H03K19/0013 ,  H01L27/1225 ,  H01L27/124 ,  H01L29/24 ,  H01L29/7869 ,  H03K19/09441 ,  H03K19/1737 ,  H03K19/17728 ,  H03K19/17748 ,  H03K19/1776

    Abstract: A programmable logic device includes a plurality of programmable logic elements (PLE) whose electrical connection is controlled by first configuration data. Each of The PLEs includes an LUT in which a relationship between a logic level of an input signal and a logic level of an output signal is determined by second configuration data, an FF to which the output signal of the LUT is input, and an MUX. The MUX includes at least two switches each including first and second transistor. A signal including third configuration data is input to a gate of the second transistor through the first transistor. The output signal of the LUT or an output signal of the FF is input to one of a source and a drain of the second transistor.

    Abstract translation: 可编程逻辑器件包括多个可编程逻辑元件（PLE），其电连接由第一配置数据来控制。 每个PLE包括LUT，其中输入信号的逻辑电平和输出信号的逻辑电平之间的关系由第二配置数据确定，输入LUT的输出信号的FF和MUX 。 MUX包括至少两个开关，每个开关包括第一和第二晶体管。 包括第三配置数据的信号通过第一晶体管输入到第二晶体管的栅极。 LUT的输出信号或FF的输出信号被输入到第二晶体管的源极和漏极之一。

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