公开(公告)号：US20190278145A1

公开(公告)日：2019-09-12

申请号：US16336490

申请日：2017-09-22

Applicant: Sharp Kabushiki Kaisha

Inventor： Kohhei TANAKA ,  Tomohiro KIMURA ,  Takayuki NISHIYAMA ,  Ryo YONEBAYASHI

IPC: G02F1/1362 ,  G02F1/1345 ,  G02F1/1368 ,  G09G3/36 ,  G02F1/1335 ,  G02F1/1343

Abstract: The invention provides a display panel that achieves narrowing at least a frame region provided with a drive circuit configured to supply a data signal. The display panel includes an active matrix substrate (10) and a counter substrate. The active matrix substrate (10) includes a data signal supplier (14) configured to supply a data signal to the frame region provided with first ends of data lines (12). The active matrix substrate (10) further includes connection lines (120P) connected to the data signal supplier (14) in the frame region. The data lines (12) include data lines (12P) connected to the data signal supplier (14) via the connection lines (120P).

公开(公告)号：US20170047034A1

公开(公告)日：2017-02-16

申请号：US15307049

申请日：2015-04-27

Applicant: SHARP KABUSHIKI KAISHA

Inventor： Takayuki NISHIYAMA ,  Kohhei TANAKA ,  Takeshi NOMA ,  Ryo YONEBAYASHI

IPC: G09G3/36 ,  G02F1/1343 ,  G02F1/1368 ,  G02F1/1362

CPC classification number: G09G3/3677 ,  G02F1/134309 ,  G02F1/136286 ,  G02F1/1368 ,  G02F2001/136295 ,  G02F2201/121 ,  G02F2201/123 ,  G09G3/3688 ,  G09G2300/0426 ,  G09G2300/0809 ,  G09G2310/0281 ,  G09G2310/08 ,  G09G2320/0209 ,  G09G2330/021

Abstract: Provided is a display device causing less noise on a signal. A display device (10) includes a plurality of signal lines (SL), a plurality of gate lines (GL), and a driving unit. The plurality of gate lines crosses the plurality of signal lines. The driving unit is connected to the plurality of gate lines and controls a potential of each of the gate lines. The driving unit includes a plurality of gate drivers (11) and a plurality of lines. The gate drivers are disposed in a display region, and at least one of the gate drivers is connected to each of the gate lines. The lines are each provided with a potential for operation of one of the gate drivers. Each of the lines crosses one of the signal lines. The plurality of lines includes a first line (17A) and a second line (17B). The driving unit switches a potential of the first line at predetermined timing. The driving unit switches a potential of the second line into a direction opposite to a direction of the switched potential of the first line upon switching the potential of the first line.

Abstract translation: 提供了对信号产生较少噪声的显示装置。 显示装置（10）包括多条信号线（SL），多条栅极线（GL）和驱动单元。 多条栅极线与多条信号线交叉。 驱动单元连接到多条栅极线并控制每条栅极线的电位。 驱动单元包括多个栅极驱动器（11）和多条线。 栅极驱动器被布置在显示区域中，并且至少一个栅极驱动器连接到每个栅极线。 这些线路各自具有用于其中一个栅极驱动器的操作的可能性。 每条线穿过信号线之一。 多条线包括第一线（17A）和第二线（17B）。 驱动单元在预定定时切换第一行的电位。 在切换第一线的电位时，驱动单元将第二线的电位切换成与第一线的开关电位的方向相反的方向。

公开(公告)号：US20200027417A1

公开(公告)日：2020-01-23

申请号：US16495458

申请日：2018-03-27

Applicant: Sharp Kabushiki Kaisha

Inventor： Tokihiro YOKONO ,  Takayuki NISHIYAMA ,  Ryo YONEBAYASHI ,  Kohhei TANAKA

IPC: G09G3/36 ,  G02F1/1335

Abstract: The invention provides a technique inhibiting luminance unevenness among pixels. An active matrix substrate has a plurality of pixel electrodes PXB each connected to a corresponding one of gate lines 13 and a corresponding one of source lines 15. The active matrix substrate includes a common electrode 14 facing each of the pixel electrodes PXB, and an auxiliary line 17 connected to the common electrode 14. The active matrix substrate further includes a plurality of drive circuits disposed in part of a display region and each configured to drive a corresponding one of the gate lines 13. The drive circuits are each connected to a control line provided for supply of a drive signal. The drive signal has first potential and second potential lower than the first potential alternately at constant cycles. The control line has a line portion 161 extending substantially in parallel with the gate lines 13. Between the line portion 161 and a capacitance forming region r where each of the pixel electrodes PXB connected to gate lines 13(n) and 13(n+2) switched into an unselected state during potential decrease of the line portion 161 forms capacitance between the pixel electrode PXB and the common electrode 14, the auxiliary line 17 is connected with the common electrode 14.

公开(公告)号：US20180039146A1

公开(公告)日：2018-02-08

申请号：US15555118

申请日：2016-03-02

Applicant: Sharp Kabushiki Kaisha

Inventor： Kohhei TANAKA ,  Takeshi NOMA ,  Takayuki NISHIYAMA ,  Ryo YONEBAYASHI

IPC: G02F1/1362 ,  G02F1/1345 ,  G09G3/36 ,  G02F1/1335

CPC classification number: G02F1/136286 ,  G02F1/133514 ,  G02F1/1343 ,  G02F1/134309 ,  G02F1/134336 ,  G02F1/13452 ,  G02F1/1362 ,  G02F1/1368 ,  G09G3/2092 ,  G09G3/36 ,  G09G3/3648 ,  G09G2300/0426 ,  G09G2300/0452 ,  G09G2310/0281 ,  G09G2310/08

Abstract: Provided is an active matrix substrate having a narrower frame region, the active matrix substrate having a display region in which a plurality of pixel regions that have pixel groups independent from one another, respectively, are arrayed along the gate lines. An active matrix substrate 20a has a display region 200 in which a pixel region 201A and a pixel region 201B that include gate lines and source lines, respectively, are arrayed along a direction in which the gate lines extend. In the pixel region 201A and the pixel region 201B, gate drivers 11 for driving gate lines 13 in the pixel regions are provided. In a frame region R1, a terminal part 12s for supplying data signals to the data lines are provided. One-side ends of data lines 15a in the pixel region 201A are routed from the terminal part 12s, and the data lines 15b in the pixel region 201A are connected with the data lines 15a in the pixel region 201A.

公开(公告)号：US20170261828A1

公开(公告)日：2017-09-14

申请号：US15528498

申请日：2015-11-19

Applicant: SHARP KABUSHIKI KAISHA

Inventor： Takeshi NOMA ,  Kohhei TANAKA ,  Takayuki NISHIYAMA ,  Ryo YONEBAYASHI

IPC: G02F1/1362 ,  G09G3/36 ,  G02F1/1368

CPC classification number: G02F1/136286 ,  G02F1/13454 ,  G02F1/1368 ,  G02F2201/123 ,  G02F2201/56 ,  G09F9/00 ,  G09F9/30 ,  G09G3/3648 ,  G09G3/3677 ,  G09G3/3688 ,  G09G2300/0426 ,  G09G2300/0804 ,  G09G2310/0286 ,  G09G2310/08 ,  G11C19/28

Abstract: Provided is an active matrix substrate that includes gate lines (13G), source lines, pixel switching elements, a plurality of gate line driving circuits (11) that control potentials of the gate lines, in the display region, and control signal lines (15L1) that supply a control signal to the gate line driving circuits (11). Each of the gate line driving circuits (11) includes driving switching elements and a capacitor. At least part of the driving switching elements and the capacitor are arranged at positions closer to, not the gate line (13G) corresponding to the gate line driving circuit (11), but another gate line (13G).

公开(公告)号：US20160370635A1

公开(公告)日：2016-12-22

申请号：US15253152

申请日：2016-08-31

Applicant: Sharp Kabushiki Kaisha

Inventor： Kohei TANAKA ,  Hidefumi YOSHIDA ,  Takeshi NOMA ,  Ryo YONEBAYASHI ,  Takayuki NISHIYAMA ,  Mitsuhiro MURATA ,  Yosuke IWATA

IPC: G02F1/1345 ,  G02F1/1362 ,  G02F1/1335 ,  G02F1/1333 ,  H01L27/12 ,  G02F1/1368

CPC classification number: G05F1/467 ,  G02F1/133308 ,  G02F1/133514 ,  G02F1/13454 ,  G02F1/136213 ,  G02F1/136227 ,  G02F1/136286 ,  G02F1/1368 ,  G02F2201/123 ,  G09G3/3677 ,  G09G2300/0408 ,  G09G2300/0426 ,  G09G2310/0251 ,  G09G2310/0281 ,  G09G2310/0286 ,  G09G2320/0223 ,  H01L27/124 ,  H01L27/1255 ,  H01L27/3272 ,  H03K17/04206 ,  H03K17/165 ,  H03K17/687

Abstract: A technique is provided that reduces dullness of a potential provided to a line such as gate line on an active-matrix substrate to enable driving the line at high speed and, at the same time, reduces the size of the picture frame region. On an active-matrix substrate (20a) are provided gate lines (13G) and source lines. On the active-matrix substrate (20a) are further provided: gate drivers (11) each including a plurality of switching elements, at least one of which is located in a pixel region, for supplying a scan signal to a gate line (13G); and lines (15L1) each for supplying a control signal to the associated gate driver (11). A control signal is supplied by a display control circuit (4) located outside the display region to the gate drivers (11) via the lines (15L1). In response to a control signal supplied, each gate driver (11) drives the gate line (13G) to which it is connected.

公开(公告)号：US20160187739A1

公开(公告)日：2016-06-30

申请号：US14908490

申请日：2014-07-24

Applicant: SHARP KABUSHIKI KAISHA

Inventor： Yosuke IWATA ,  Mitsuhiro MURATA ,  Kouhei TANAKA ,  Tadashi OHTAKE ,  Ryo YONEBAYASHI

IPC: G02F1/1343 ,  G02F1/1368

CPC classification number: G02F1/134309 ,  G02F1/134363 ,  G02F1/1368

Abstract: A liquid crystal display device includes: a first substrate; a second substrate facing the first substrate; and a liquid crystal layer sandwiched between the first substrate and the second substrate. The first substrate has thereon a first planar electrode, a first dielectric layer on the first planar electrode, and a pair of comb-shaped electrodes on the first dielectric layer. The second substrate has thereon a second planar electrode and a second dielectric layer on the second planar electrode. The liquid crystal layer includes liquid crystal molecules having a positive dielectric anisotropy. The liquid crystal display device is configured such that, when displaying a minimum gradation, a same voltage is applied to the pair of comb-shaped electrodes, and a relationship among voltages applied to the first planar electrode, the pair of comb-shaped electrodes, and the second planar electrode satisfies a prescribed relational expression.

Abstract translation: 液晶显示装置包括：第一基板; 面对所述第一基板的第二基板; 以及夹在第一基板和第二基板之间的液晶层。 第一基板上具有第一平面电极，第一平面电极上的第一电介质层和第一介电层上的一对梳状电极。 第二基板上具有第二平面电极和第二平面电极上的第二电介质层。 液晶层包括具有正介电各向异性的液晶分子。 液晶显示装置被配置为使得当显示最小灰度时，对一对梳状电极施加相同的电压，并且施加到第一平面电极，一对梳状电极的电压之间的关系， 第二平面电极满足规定的关系式。

公开(公告)号：US20240233633A1

公开(公告)日：2024-07-11

申请号：US18559397

申请日：2021-06-17

Applicant: Sharp Kabushiki Kaisha

Inventor： Ryo YONEBAYASHI

IPC: G09G3/3225

CPC classification number: G09G3/3225 ,  G09G2300/02 ,  G09G2310/0208 ,  G09G2310/0237 ,  G09G2310/0286

Abstract: The present application discloses a current-driven display device employing an internal compensation method capable of achieving high-resolution of the display image while suppressing a reduction in the yield of manufacturing, the deterioration in display quality, an increase in the circuit amount. In a pixel circuit of an organic EL display device, a voltage of the gate terminal of a drive transistor is initialized before the voltage of a data signal line is written into a holding capacitor via the drive transistor in a diode-connected state. At this time, a current flows from the holding capacitor connected to the gate terminal of the drive transistor to an initialization voltage line via a threshold compensation transistor, a second light emission control transistor, and a display element initialization transistor, and the voltage Vg of the gate terminal is initialized. Thus, an initialization transistor provided between the gate terminal and the initialization voltage line in the related art comes to be unnecessary.

公开(公告)号：US20240203344A1

公开(公告)日：2024-06-20

申请号：US17909861

申请日：2020-04-21

Applicant: Sharp Kabushiki Kaisha

Inventor： Keiichi YAMAMOTO ,  Ryo YONEBAYASHI

IPC: G09G3/3233

CPC classification number: G09G3/3233 ,  G09G2300/0819 ,  G09G2300/0842 ,  G09G2300/0861 ,  G09G2310/08 ,  G09G2320/0238 ,  G09G2320/045 ,  G09G2330/021

Abstract: A display device is implemented that can reduce power consumption over a known example while preventing occurrence of black floating. The voltage value of a low-level power supply voltage ELVSS provided to a pixel circuit is set to a higher value in a pause driving period than in a normal driving period. Upon writing a data voltage, an anode initialization period for initializing an anode voltage of an organic EL element is provided. In this regard, an anode initialization period in the pause driving period is made longer than an anode initialization period in the normal driving period. To implement this, for example, a write frequency of a data voltage is made lower in the pause driving period than in the normal driving period.

公开(公告)号：US20240087520A1

公开(公告)日：2024-03-14

申请号：US18274731

申请日：2021-02-01

Applicant: Sharp Kabushiki Kaisha

Inventor： Kuniaki OKADA ,  Ryo YONEBAYASHI

IPC: G09G3/3233

CPC classification number: G09G3/3233 ,  G09G2300/0819 ,  G09G2300/0842 ,  G09G2300/0861 ,  G09G2310/0262 ,  G09G2310/08 ,  G09G2320/0238 ,  G09G2320/045

Abstract: The present application discloses a display device capable of preventing a black display defect with a pixel circuit used therein in which P-type and N-type transistors are mixed. Provided is a pixel circuit including an organic EL element, a holding capacitor, a P-type drive transistor, a P-type writing control transistor, an N-type threshold compensation transistor, and the like, wherein during a data writing period, the voltage of a data signal line is written to the holding capacitor via the writing control transistor in ON state and the drive transistor brought into a diode-connected state by the threshold compensation transistor in ON state. A capacitance is provided between a first scanning signal line connected to a gate terminal of the writing control transistor and a gate terminal of the drive transistor. Consequently, when the P-type writing control transistor is turned off at the end of a data write period, a gate voltage Vg of the drive transistor increases, and this increase compensates for a decrease in the gate voltage Vg occurring when the N-type threshold compensation transistor is thereafter turned off.