公开(公告)号：US20240357836A1

公开(公告)日：2024-10-24

申请号：US18758786

申请日：2024-06-28

Applicant: SK hynix Inc.

Inventor： Jae Hyun HAN ,  Se Ho LEE ,  Hyangkeun YOO

IPC: H10B63/00 ,  H10N70/00 ,  H10N70/20

CPC classification number: H10B63/30 ,  H10B63/82 ,  H10B63/84 ,  H10N70/24 ,  H10N70/245 ,  H10N70/253 ,  H10N70/823 ,  H10N70/841 ,  H10N70/8822 ,  H10N70/8828 ,  H10N70/883 ,  H10N70/8833 ,  H10N70/8836

Abstract: A nonvolatile memory device according to an embodiment includes a substrate, a resistance change layer disposed on the substrate, a gate electrode layers disposed on the resistance change layer, and a first electrode pattern layer and a second electrode pattern layer that are disposed in the substrate and contact different portions of the resistance change layer. The resistance change layer includes movable oxygen vacancies or movable metal ions.

公开(公告)号：US20230359393A1

公开(公告)日：2023-11-09

申请号：US18084930

申请日：2022-12-20

Applicant: SK hynix Inc.

Inventor： Se Ho LEE ,  Min Gu KANG

IPC: G06F3/06

CPC classification number: G06F3/0659 ,  G06F3/0658 ,  G06F3/0607 ,  G06F3/0679

Abstract: A memory system includes a non-volatile memory device and a performance manager. The performance manager activates a plurality of sub-controllers according to a setting of a host device, allocates memory regions respectively to the plurality of sub-controllers, the memory regions being included in the non-volatile memory device, and determines, according to maximum performance values and a size ratio of the memory regions, credit sets to be allocated respectively to the plurality of sub-controllers.

公开(公告)号：US20220399371A1

公开(公告)日：2022-12-15

申请号：US17892514

申请日：2022-08-22

Applicant: SK hynix Inc.

Inventor： Jae Hyun HAN ,  Jae Gil LEE ,  Hyangkeun YOO ,  Se Ho LEE

IPC: H01L27/11597 ,  H01L27/11587 ,  H01L29/786 ,  H01L29/78 ,  H01L29/788

Abstract: A nonvolatile memory device includes a substrate having an upper surface, and a gate structure disposed over the substrate. The gate structure includes at least one gate electrode layer pattern and at least one gate insulation layer pattern, which are alternately stacked along a first direction perpendicular to the upper surface. The gate structure extends in a second direction perpendicular to the first direction. The nonvolatile memory device includes a ferroelectric layer disposed on at least a portion of one sidewall surface of the gate structure. The one sidewall surface of the gate structure forms a plane substantially parallel to the first and second directions. The nonvolatile memory device includes a channel layer disposed on the ferroelectric layer, and a source electrode structure and a drain electrode structure disposed to contact the channel layer and spaced apart from each other in the second direction.

公开(公告)号：US20220376092A1

公开(公告)日：2022-11-24

申请号：US17878893

申请日：2022-08-01

Applicant: SK hynix Inc.

Inventor： Bo Yun KIM ,  Se Ho LEE

IPC: H01L29/66 ,  H01L27/11582 ,  H01L21/02 ,  H01L29/792

Abstract: In a method of fabricating a nonvolatile memory device according an embodiment, a first tunnel oxide layer, a nitrogen supply layer, and a second tunnel oxide layer having a density lower than that of the first tunnel oxide layer are formed on a substrate. Nitrogen in the nitrogen supply layer is diffused into the second tunnel oxide layer to convert at least a portion of the second tunnel oxide layer into an oxynitride layer.

公开(公告)号：US20220189972A1

公开(公告)日：2022-06-16

申请号：US17317663

申请日：2021-05-11

Applicant: SK hynix Inc.

Inventor： Jae Gil LEE ,  Dong Ik SUH ,  Se Ho LEE

IPC: H01L27/1159 ,  G11C11/22

Abstract: A semiconductor device according to an embodiment includes a substrate, a bit line structure and a source line structure respectively extending in a direction perpendicular to a surface of the substrate, a semiconductor layer disposed between the bit line structure and the source line structure on a plane parallel to the surface of the substrate, a first ferroelectric layer disposed on a first surface of the semiconductor layer, and a first gate electrode layer disposed on the first ferroelectric layer.

公开(公告)号：US20210175252A1

公开(公告)日：2021-06-10

申请号：US16891469

申请日：2020-06-03

Applicant: SK hynix Inc.

Inventor： Jae Hyun HAN ,  Se Ho LEE ,  Hyangkeun YOO ,  Jae Gil LEE

IPC: H01L27/11597 ,  H01L29/78 ,  H01L29/788

Abstract: A nonvolatile memory device according to an embodiment includes a substrate having an upper surface, a source electrode structure disposed on the substrate, and a channel structure disposed over the substrate and disposed to contact one sidewall surface of the source electrode structure. In addition, the nonvolatile memory device includes a drain electrode structure disposed to contact one sidewall surface of the channel structure over the substrate. In addition, the nonvolatile memory device includes a plurality of ferroelectric structures extending in a first direction perpendicular to the substrate in the channel structure and disposed to be spaced apart from each other along the second direction perpendicular to the first direction. In addition, the nonvolatile memory device includes a gate electrode structure disposed in each of the plurality of ferroelectric structure to extend along the first direction.

公开(公告)号：US20150103589A1

公开(公告)日：2015-04-16

申请号：US14173542

申请日：2014-02-05

Applicant: SK hynix Inc.

Inventor： Se Ho LEE

IPC: G11C13/00

CPC classification number: G11C13/004 ,  G11C11/5678 ,  G11C13/0002 ,  G11C13/0004 ,  G11C13/0038 ,  G11C13/0064 ,  G11C13/0069

Abstract: A resistive memory apparatus includes a memory cell array including a plurality of resistive memory cells, an address decoder suitable for decoding an address signal, and accessing the memory cell array, a read/write control circuit suitable for programming data in the memory cell array or reading out data from the memory cell array, a voltage generation unit suitable for generating a program voltage and a first read voltage for a program operation and a second read voltage for a read operation and providing the voltages to the address decoder, and a controller suitable for controlling the voltage generation unit to generate the first read voltage for verification of the program operation in response to a program command, and the second read voltage higher than the first voltage in response to a read command.

Abstract translation: 电阻式存储装置包括存储单元阵列，该存储单元阵列包括多个电阻存储器单元，适用于解码地址信号的地址解码器，以及访问存储单元阵列，适于在存储单元阵列中编程数据的读/写控制电路， 从存储单元阵列读出数据，适用于产生用于编程操作的编程电压和第一读取电压的电压产生单元，以及用于读取操作的第二读取电压，并向地址解码器提供电压，以及适于 用于响应于读取命令，控制电压产生单元以响应于程序命令产生用于验证编程操作的第一读取电压，以及高于第一电压的第二读取电压。

公开(公告)号：US20140325120A1

公开(公告)日：2014-10-30

申请号：US14043524

申请日：2013-10-01

Applicant: SK hynix Inc.

Inventor： Hae Chan PARK ,  Myoung Sub KIM ,  Se Ho LEE ,  Seung Yun LEE

IPC: G11C13/00

CPC classification number: G11C13/003 ,  G11C11/5678 ,  G11C13/0004 ,  G11C13/0007 ,  G11C13/0033 ,  G11C13/004 ,  G11C13/0064 ,  G11C13/0069 ,  G11C13/0097 ,  G11C2013/0073 ,  G11C2013/0092 ,  G11C2213/15 ,  G11C2213/73

Abstract: A resistive memory device includes a memory cell array including a unit memory cell coupled between a word line and a bit line, wherein the unit memory cell includes a data storage material and a non-silicon-substrate-based type bidirectional access device coupled in series, a path setting circuit coupled between the bit line and the word line, suitable for providing a program pulse toward the bit line or the word line based on a path control signal, a forward write command, and a reverse write command, and a control unit suitable for providing a write path control signal, a forward program command, and a reverse program command based on an external command signal.

Abstract translation: 电阻式存储器件包括存储单元阵列，该存储单元阵列包括耦合在字线和位线之间的单元存储单元，其中单元存储单元包括数据存储材料和基于非硅基的类型的双向存取器件，其串联连接 耦合在位线和字线之间的路径设置电路，适于基于路径控制信号，前向写入命令和反向写入命令向位线或字线提供编程脉冲，以及控制 适用于提供基于外部命令信号的写入路径控制信号，正向编程命令和反向编程命令的单元。

公开(公告)号：US20130094285A1

公开(公告)日：2013-04-18

申请号：US13706745

申请日：2012-12-06

Applicant: SK HYNIX INC.

Inventor： Hae Chan PARK ,  Se Ho LEE

IPC: G11C11/21

CPC classification number: G11C13/0004 ,  G11C11/21 ,  G11C11/5678 ,  G11C13/0028 ,  G11C13/003 ,  G11C13/004 ,  G11C13/0069 ,  G11C2013/0042 ,  G11C2013/0078 ,  G11C2213/71 ,  G11C2213/72 ,  G11C2213/74 ,  H01L45/04

Abstract: A phase change memory device having a multi-level and a method of driving the same are presented. The disclosed phase change memory device includes variable resistors and shifting units. The variable resistors are interchanged into set and reset states in response to an applied current. The shifting units, which are connected to the variable resistors, shift resistance distribution in the set and reset state of the variable resistors by a predetermined level.

公开(公告)号：US20230098622A1

公开(公告)日：2023-03-30

申请号：US17749127

申请日：2022-05-19

Applicant: SK hynix Inc.

Inventor： Won Tae KOO ,  Dong Ik SUH ,  Se Ho LEE

IPC: H01L27/11507

Abstract: A semiconductor device includes a first electrode, a ferroelectric layer disposed on the first electrode and implementing a negative capacitance, a dielectric structure disposed on the ferroelectric layer and including a first dielectric layer and a second dielectric layer that are alternately stacked, and a second electrode disposed on the dielectric structure. The ferroelectric layer and the dielectric structure are configured to be electrically connected in series to each other. The ferroelectric layer and dielectric structure together have a non-ferroelectric property.