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    DELAY CIRCUIT AND SEMICONDUCTOR APPARATUS INCLUDING THE SAME
    11.
    发明申请
    DELAY CIRCUIT AND SEMICONDUCTOR APPARATUS INCLUDING THE SAME 有权
    延迟电路和半导体器件包括它们

    公开(公告)号：US20140002154A1

    公开(公告)日：2014-01-02

    申请号：US13712625

    申请日：2012-12-12

    Applicant: SK HYNIX INC.

    Inventor： Jae Min JANG ,  Yong Ju KIM ,  Dae Han KWON ,  Hae Rang CHOI

    IPC: H03L7/08

    CPC classification number: H03L7/08 ,  H03L7/0805 ,  H03L7/0814 ,  H03L7/0816 ,  H03L7/093

    Abstract: A delay circuit includes a clock delay line, a command delay line, a delay line control block, and a shared shift register block. The clock delay line delays an input clock and generates a delayed clock. The command delay line delays a command signal and generates a delayed command signal. The delay line control block generates a control signal according to a result of comparing phases of a feedback clock which is generated as the delayed clock is delayed by a modeled delay value and the input clock. The shared shift register block sets delay amounts of the clock delay line and the command delay line to be substantially the same with each other, in response to the control signal.

    Abstract translation: 延迟电路包括时钟延迟线，命令延迟线，延迟线控制块和共享移位寄存器块。 时钟延迟线延迟输入时钟并产生延迟时钟。 命令延迟线延迟命令信号并产生延迟命令信号。 延迟线控制块根据比较由延迟时钟延迟建模延迟值和输入时钟而产生的反馈时钟的相位的结果产生控制信号。 响应于控制信号，共享移位寄存器块将时钟延迟线和命令延迟线的延迟量设定为彼此基本相同。

    DELAY CONTROL CIRCUIT AND CLOCK GENERATION CIRCUIT INCLUDING THE SAME
    12.
    发明申请
    DELAY CONTROL CIRCUIT AND CLOCK GENERATION CIRCUIT INCLUDING THE SAME 有权
    延迟控制电路和时钟发生电路，包括它们

    公开(公告)号：US20130342250A1

    公开(公告)日：2013-12-26

    申请号：US13711750

    申请日：2012-12-12

    Applicant: SK HYNIX INC.

    Inventor： Dae Han KWON ,  Yong Ju KIM ,  Jae Min JANG ,  Hae Rang CHOI

    IPC: H03L7/085

    CPC classification number: H03L7/085 ,  H03L7/0814 ,  H03L7/0816 ,  H03L7/093 ,  H03L7/095 ,  H03L7/10

    Abstract: A clock generation circuit includes a delay line, which delays an input clock and generates a delayed clock, a delay modeling unit, which delays the delayed clock by a modeled delay value and generates a feedback clock, a phase detection unit, which compares phases of the input clock and the feedback clock and generates a phase detection signal, a filter unit, which receives the phase detection signal and generates phase information, generates an update signal when a difference between the numbers of phase detection signals with a first and a second level generated is greater than or equal to a threshold value, and generates the update signal after a lapse of a predetermined time when the difference is less than the threshold value, and a delay line control unit, which sets a delay value of the delay line in response to the update signal and the phase information.

    Abstract translation: 时钟生成电路包括延迟输入时钟并产生延迟时钟的延迟线，延迟建模单元，其通过建模延迟值延迟延迟时钟并产生反馈时钟，相位检测单元，其比较 输入时钟和反馈时钟，并产生相位检测信号，滤波器单元，其接收相位检测信号并产生相位信息，当相位检测信号的数量与第一和第二电平之间的差异产生更新信号 产生的阈值大于或等于阈值，并且在差小于阈值的经过预定时间之后生成更新信号;以及延迟线控制单元，其将延迟线的延迟值设置在 对更新信号和相位信息的响应。

    SEMICONDUCTOR DEVICE FOR CALCULATING AND CALIBRATING DELAY AMOUNT
    13.
    发明公开
    SEMICONDUCTOR DEVICE FOR CALCULATING AND CALIBRATING DELAY AMOUNT 审中-公开

    公开(公告)号：US20230282256A1

    公开(公告)日：2023-09-07

    申请号：US17858519

    申请日：2022-07-06

    Applicant: SK hynix Inc.

    Inventor： Gi Moon HONG ,  Dae Han KWON

    IPC: G11C7/22 ,  H03K5/133

    CPC classification number: G11C7/222 ,  H03K5/133

    Abstract: A semiconductor device includes a strobe transmission circuit configured to output an oscillation strobe signal, through a first delay path circuit, as a strobe signal when a first measurement operation is performed and configured to output the oscillation strobe signal through a second delay path circuit as the strobe signal when a second measurement operation is performed, and a calibration circuit configured to compare the number of times the strobe signal toggles during the first measurement operation to the number of times the strobe signal toggles during the second measurement operation to calibrate the delay amounts of the first and second delay path circuits to be the same.

    BUFFERING CIRCUIT, AND SEMICONDUCTOR APPARATUS AND SYSTEM INCLUDING BUFFERING CIRCUIT
    17.
    发明申请
    BUFFERING CIRCUIT, AND SEMICONDUCTOR APPARATUS AND SYSTEM INCLUDING BUFFERING CIRCUIT 审中-公开

    公开(公告)号：US20190252013A1

    公开(公告)日：2019-08-15

    申请号：US16218181

    申请日：2018-12-12

    Applicant: SK hynix Inc.

    Inventor： Kyu Dong HWANG ,  Dae Han KWON

    IPC: G11C7/22 ,  G11C7/10

    Abstract: A buffering circuit includes a first signal input/output unit that generates an output bar signal in response to an input signal, a second signal input/output unit that generates an output signal in response to an input bar signal, and a connection unit that electrically connects and disconnects an output node of the first signal input/output unit and a current sink node of the second signal input/output unit to/from each other in response to a control signal, and electrically connects and disconnects a current sink node of the first signal input/output unit and an output node of the second signal input/output unit to/from each other in response to the control signal.

    SEMICONDUCTOR MEMORY APPARATUS
    18.
    发明申请
    SEMICONDUCTOR MEMORY APPARATUS 有权
    半导体存储器

    公开(公告)号：US20140293689A1

    公开(公告)日：2014-10-02

    申请号：US14301458

    申请日：2014-06-11

    Applicant: SK hynix Inc.

    Inventor： Taek Sang SONG ,  Dae Han KWON

    IPC: G11C13/00

    CPC classification number: G11C11/00 ,  G11C7/14 ,  G11C13/0004 ,  G11C13/004 ,  G11C2013/0045 ,  G11C2013/0054

    Abstract: A semiconductor memory apparatus includes a resistive memory cell; a data sensing unit configured to sense an output voltage, formed by a sensing current supplied to the resistive memory cell, based on a reference voltage, and output data having a value corresponding to the sensing result; and a reference voltage generation unit comprising a dummy memory cell including first and second resistors having first and second resistance values, respectively, and configured to output a voltage formed by the sensing current supplied to the dummy memory cell as the reference voltage.

    Abstract translation: 半导体存储装置包括电阻式存储单元; 数据感测单元，被配置为基于参考电压感测由提供给所述电阻性存储单元的感测电流形成的输出电压，以及输出具有与所述感测结果对应的值的数据; 以及参考电压产生单元，包括分别包括具有第一和第二电阻值的第一和第二电阻器的虚拟存储单元，并且被配置为输出由提供给虚拟存储单元的感测电流形成的电压作为参考电压。

    RESET SIGNAL GENERATION APPARATUS
    19.
    发明申请
    RESET SIGNAL GENERATION APPARATUS 有权
    复位信号发生装置

    公开(公告)号：US20130342245A1

    公开(公告)日：2013-12-26

    申请号：US13720943

    申请日：2012-12-19

    Applicant: SK HYNIX INC.

    Inventor： Jae Min JANG ,  Yong Ju KIM ,  Dae Han KWON ,  Hae Rang CHOI

    IPC: H03K3/011

    CPC classification number: H03K3/011 ,  G06F1/24 ,  H03K5/05

    Abstract: A reset signal generation apparatus includes a reset signal generation unit and a reset signal expansion unit. The reset signal generation unit enables a reset signal and an enable signal in response to a reset input signal, and disables the reset signal in response to a pulse width extension signal. The reset signal expansion unit generates the pulse width extension signal that is enabled for a predetermined time, in response to the enable signal.

    Abstract translation: 复位信号发生装置包括复位信号生成单元和复位信号扩展单元。 复位信号生成单元响应于复位输入信号启用复位信号和使能信号，并且响应于脉冲宽度扩展信号而禁用复位信号。 复位信号扩展单元响应于使能信号产生使能了预定时间的脉宽扩展信号。

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