中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

15 records (took 0.012 seconds)

    RESET SIGNAL GENERATION APPARATUS
    2.
    发明申请
    RESET SIGNAL GENERATION APPARATUS 有权
    复位信号发生装置

    公开(公告)号：US20130342245A1

    公开(公告)日：2013-12-26

    申请号：US13720943

    申请日：2012-12-19

    Applicant: SK HYNIX INC.

    Inventor： Jae Min JANG ,  Yong Ju KIM ,  Dae Han KWON ,  Hae Rang CHOI

    IPC: H03K3/011

    CPC classification number: H03K3/011 ,  G06F1/24 ,  H03K5/05

    Abstract: A reset signal generation apparatus includes a reset signal generation unit and a reset signal expansion unit. The reset signal generation unit enables a reset signal and an enable signal in response to a reset input signal, and disables the reset signal in response to a pulse width extension signal. The reset signal expansion unit generates the pulse width extension signal that is enabled for a predetermined time, in response to the enable signal.

    Abstract translation: 复位信号发生装置包括复位信号生成单元和复位信号扩展单元。 复位信号生成单元响应于复位输入信号启用复位信号和使能信号，并且响应于脉冲宽度扩展信号而禁用复位信号。 复位信号扩展单元响应于使能信号产生使能了预定时间的脉宽扩展信号。

    PROCESSING-IN-MEMORY DEVICES
    3.
    发明申请
    PROCESSING-IN-MEMORY DEVICES 有权

    公开(公告)号：US20250022503A1

    公开(公告)日：2025-01-16

    申请号：US18420019

    申请日：2024-01-23

    Applicant: SK hynix Inc.

    Inventor： Hae Rang CHOI

    IPC: G11C11/4091 ,  G11C11/408 ,  G11C11/4096

    Abstract: A processing-in-memory device includes a memory cell array including a plurality of memory cells coupled to a plurality of word lines and a plurality of bit lines, a sense amplifier circuit coupled to the plurality of bit lines, and a control circuit configured to perform a row data copy operation that copies data of a first word line to a second word line, among the plurality of word lines. The control circuit is configured to sequentially perform operations according to an active control signal, a row close control signal, and a row open control signal to perform the row data copy operation.

    CLOCK GENERATION CIRCUIT AND SEMICONDUCTOR APPARATUS INCLUDING THE SAME
    7.
    发明申请
    CLOCK GENERATION CIRCUIT AND SEMICONDUCTOR APPARATUS INCLUDING THE SAME 有权
    时钟发生电路和半导体器件包括它们

    公开(公告)号：US20140002149A1

    公开(公告)日：2014-01-02

    申请号：US13711692

    申请日：2012-12-12

    Applicant: SK HYNIX INC.

    Inventor： Jae Min JANG ,  Yong Ju KIM ,  Dae Han KWON ,  Hae Rang CHOI

    IPC: H03H11/26 ,  H03L7/06

    CPC classification number: H03H11/265 ,  H03L7/06 ,  H03L7/0814 ,  H03L7/0816 ,  H03L7/0818 ,  H03L7/085

    Abstract: A clock generation circuit includes a delay line, a delay modeling block, a phase detection block, a multi-update signal generation block, and a delay line. The delay line delays an input clock and generates a delayed clock. The delay modeling block delays the delayed clock by a modeled delay value and generates a feedback clock. The phase detection block compares phases of the input clock and the feedback clock and generates phase information, and quantizes a phase difference between the input clock and the feedback clock and generates phase codes. The multi-update signal generation block generates a multi-update signal in response to the phase codes. The delay line control block changes a delay amount of the delay line in response to the multi-update signal and the phase information.

    Abstract translation: 时钟生成电路包括延迟线，延迟建模块，相位检测块，多更新信号生成块和延迟线。 延迟线延迟输入时钟并产生延迟时钟。 延迟建模块通过建模延迟值将延迟时钟延迟并产生反馈时钟。 相位检测块比较输入时钟和反馈时钟的相位，并产生相位信息，并量化输入时钟和反馈时钟之间的相位差，并产生相位代码。 多更新信号生成块响应于相位代码生成多更新信号。 响应于多更新信号和相位信息，延迟线控制块改变延迟线的延迟量。

    CURRENT GENERATION CIRCUITS AND SEMICONDUCTOR DEVICES INCLUDING THE SAME
    8.
    发明申请
    CURRENT GENERATION CIRCUITS AND SEMICONDUCTOR DEVICES INCLUDING THE SAME 有权
    电流发生电路和包括其的半导体器件

    公开(公告)号：US20150236579A1

    公开(公告)日：2015-08-20

    申请号：US14446039

    申请日：2014-07-29

    Applicant: SK hynix Inc.

    Inventor： Hae Rang CHOI

    IPC: H02M1/08 ,  H02M3/156

    CPC classification number: G05F3/262

    Abstract: Semiconductor devices are provided. The semiconductor device may include a current generation circuit and an internal circuit. The current generation circuit may include a first drive element and a second drive element which are connected in series. The current generation circuit may generate a reference voltage signal whose voltage level is set by a reference current which is identical or substantially identical to a current flowing through the first and second drive elements. The internal circuit may utilize an output current controlled according to the reference current as an operation current thereof.

    Abstract translation: 提供半导体器件。 半导体器件可以包括电流产生电路和内部电路。 电流发生电路可以包括串联连接的第一驱动元件和第二驱动元件。 电流发生电路可以产生参考电压信号，该参考电压信号的电压电平由与第一和第二驱动元件流过的电流相同或基本相同的参考电流来设定。 内部电路可以利用根据参考电流控制的输出电流作为其工作电流。

    DELAY CIRCUIT AND SEMICONDUCTOR APPARATUS INCLUDING THE SAME
    10.
    发明申请
    DELAY CIRCUIT AND SEMICONDUCTOR APPARATUS INCLUDING THE SAME 有权
    延迟电路和半导体器件包括它们

    公开(公告)号：US20140002154A1

    公开(公告)日：2014-01-02

    申请号：US13712625

    申请日：2012-12-12

    Applicant: SK HYNIX INC.

    Inventor： Jae Min JANG ,  Yong Ju KIM ,  Dae Han KWON ,  Hae Rang CHOI

    IPC: H03L7/08

    CPC classification number: H03L7/08 ,  H03L7/0805 ,  H03L7/0814 ,  H03L7/0816 ,  H03L7/093

    Abstract: A delay circuit includes a clock delay line, a command delay line, a delay line control block, and a shared shift register block. The clock delay line delays an input clock and generates a delayed clock. The command delay line delays a command signal and generates a delayed command signal. The delay line control block generates a control signal according to a result of comparing phases of a feedback clock which is generated as the delayed clock is delayed by a modeled delay value and the input clock. The shared shift register block sets delay amounts of the clock delay line and the command delay line to be substantially the same with each other, in response to the control signal.

    Abstract translation: 延迟电路包括时钟延迟线，命令延迟线，延迟线控制块和共享移位寄存器块。 时钟延迟线延迟输入时钟并产生延迟时钟。 命令延迟线延迟命令信号并产生延迟命令信号。 延迟线控制块根据比较由延迟时钟延迟建模延迟值和输入时钟而产生的反馈时钟的相位的结果产生控制信号。 响应于控制信号，共享移位寄存器块将时钟延迟线和命令延迟线的延迟量设定为彼此基本相同。

Patent Agency Ranking