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    RESET SIGNAL GENERATION APPARATUS
    2.
    发明申请
    RESET SIGNAL GENERATION APPARATUS 有权
    复位信号发生装置

    公开(公告)号：US20130342245A1

    公开(公告)日：2013-12-26

    申请号：US13720943

    申请日：2012-12-19

    Applicant: SK HYNIX INC.

    Inventor： Jae Min JANG ,  Yong Ju KIM ,  Dae Han KWON ,  Hae Rang CHOI

    IPC: H03K3/011

    CPC classification number: H03K3/011 ,  G06F1/24 ,  H03K5/05

    Abstract: A reset signal generation apparatus includes a reset signal generation unit and a reset signal expansion unit. The reset signal generation unit enables a reset signal and an enable signal in response to a reset input signal, and disables the reset signal in response to a pulse width extension signal. The reset signal expansion unit generates the pulse width extension signal that is enabled for a predetermined time, in response to the enable signal.

    Abstract translation: 复位信号发生装置包括复位信号生成单元和复位信号扩展单元。 复位信号生成单元响应于复位输入信号启用复位信号和使能信号，并且响应于脉冲宽度扩展信号而禁用复位信号。 复位信号扩展单元响应于使能信号产生使能了预定时间的脉宽扩展信号。

    PHASE MIXING CIRCUIT, AND SEMICONDUCTOR APPARATUS AND SEMICONDUCTOR SYSTEM INCLUDING THE SAME
    4.
    发明申请
    PHASE MIXING CIRCUIT, AND SEMICONDUCTOR APPARATUS AND SEMICONDUCTOR SYSTEM INCLUDING THE SAME 有权
    相混合电路和包括它们的半导体装置和半导体系统

    公开(公告)号：US20150054558A1

    公开(公告)日：2015-02-26

    申请号：US14092251

    申请日：2013-11-27

    Applicant: SK hynix Inc.

    Inventor： Jae Min JANG ,  Yong Ju KIM ,  Dae Han KWON ,  Kil Ho CHA

    IPC: H03K5/13

    CPC classification number: H03K5/131

    Abstract: A phase mixing circuit includes a first mixing unit configured to mix phases of first and second clocks at a predetermined ratio, and generate a first mixed signal; a second mixing unit configured to mix phases of an inverted signal of the first clock and an inverted signal of the second clock at the predetermined ratio, and generate a second mixed signal; and an output unit configured to generate an output signal based on of the first and second mixed signals.

    Abstract translation: 相位混合电路包括：第一混合单元，被配置为以预定比率混合第一和第二时钟的相位，并产生第一混合信号; 第二混合单元，被配置为以预定比率混合第一时钟的反相信号的相位和第二时钟的反相信号，并产生第二混合信号; 以及输出单元，被配置为基于第一和第二混合信号产生输出信号。

    CLOCK GENERATION CIRCUIT AND SEMICONDUCTOR APPARATUS INCLUDING THE SAME
    5.
    发明申请
    CLOCK GENERATION CIRCUIT AND SEMICONDUCTOR APPARATUS INCLUDING THE SAME 有权
    时钟发生电路和半导体器件包括它们

    公开(公告)号：US20140002149A1

    公开(公告)日：2014-01-02

    申请号：US13711692

    申请日：2012-12-12

    Applicant: SK HYNIX INC.

    Inventor： Jae Min JANG ,  Yong Ju KIM ,  Dae Han KWON ,  Hae Rang CHOI

    IPC: H03H11/26 ,  H03L7/06

    CPC classification number: H03H11/265 ,  H03L7/06 ,  H03L7/0814 ,  H03L7/0816 ,  H03L7/0818 ,  H03L7/085

    Abstract: A clock generation circuit includes a delay line, a delay modeling block, a phase detection block, a multi-update signal generation block, and a delay line. The delay line delays an input clock and generates a delayed clock. The delay modeling block delays the delayed clock by a modeled delay value and generates a feedback clock. The phase detection block compares phases of the input clock and the feedback clock and generates phase information, and quantizes a phase difference between the input clock and the feedback clock and generates phase codes. The multi-update signal generation block generates a multi-update signal in response to the phase codes. The delay line control block changes a delay amount of the delay line in response to the multi-update signal and the phase information.

    Abstract translation: 时钟生成电路包括延迟线，延迟建模块，相位检测块，多更新信号生成块和延迟线。 延迟线延迟输入时钟并产生延迟时钟。 延迟建模块通过建模延迟值将延迟时钟延迟并产生反馈时钟。 相位检测块比较输入时钟和反馈时钟的相位，并产生相位信息，并量化输入时钟和反馈时钟之间的相位差，并产生相位代码。 多更新信号生成块响应于相位代码生成多更新信号。 响应于多更新信号和相位信息，延迟线控制块改变延迟线的延迟量。

    MEMORY CONTROLLER INCLUDING MEMORY MANAGER FOR MAPPING BUFFER IDNENTIFIER TO SEGMENT
    6.
    发明公开
    MEMORY CONTROLLER INCLUDING MEMORY MANAGER FOR MAPPING BUFFER IDNENTIFIER TO SEGMENT 审中-公开

    公开(公告)号：US20240069796A1

    公开(公告)日：2024-02-29

    申请号：US18151429

    申请日：2023-01-07

    Applicant: SK hynix Inc.

    Inventor： Tae Ho LIM ,  Ie Ryung PARK ,  Dong Sop LEE ,  Youn Won PARK ,  Jae Min JANG

    IPC: G06F3/06

    CPC classification number: G06F3/0656 ,  G06F3/0604 ,  G06F3/0673

    Abstract: A memory controller includes a plurality of processors, a memory device and a memory manager. The memory device includes a plurality of segments, which are divided into a plurality of segment groups, to which group identifiers are respectively assigned. The memory manager is configured to map a first buffer identifier to a first group identifier from among the group identifiers, select one or more segments only from a first segment group, to which the first group identifier is assigned among the plurality of segment groups, map the first buffer identifier to the one or more segments, and allocate, to a first processor from among the plurality of processors, the first buffer identifier and the one or more segments.

    DELAY CIRCUIT AND SEMICONDUCTOR APPARATUS INCLUDING THE SAME
    8.
    发明申请
    DELAY CIRCUIT AND SEMICONDUCTOR APPARATUS INCLUDING THE SAME 有权
    延迟电路和半导体器件包括它们

    公开(公告)号：US20140002154A1

    公开(公告)日：2014-01-02

    申请号：US13712625

    申请日：2012-12-12

    Applicant: SK HYNIX INC.

    Inventor： Jae Min JANG ,  Yong Ju KIM ,  Dae Han KWON ,  Hae Rang CHOI

    IPC: H03L7/08

    CPC classification number: H03L7/08 ,  H03L7/0805 ,  H03L7/0814 ,  H03L7/0816 ,  H03L7/093

    Abstract: A delay circuit includes a clock delay line, a command delay line, a delay line control block, and a shared shift register block. The clock delay line delays an input clock and generates a delayed clock. The command delay line delays a command signal and generates a delayed command signal. The delay line control block generates a control signal according to a result of comparing phases of a feedback clock which is generated as the delayed clock is delayed by a modeled delay value and the input clock. The shared shift register block sets delay amounts of the clock delay line and the command delay line to be substantially the same with each other, in response to the control signal.

    Abstract translation: 延迟电路包括时钟延迟线，命令延迟线，延迟线控制块和共享移位寄存器块。 时钟延迟线延迟输入时钟并产生延迟时钟。 命令延迟线延迟命令信号并产生延迟命令信号。 延迟线控制块根据比较由延迟时钟延迟建模延迟值和输入时钟而产生的反馈时钟的相位的结果产生控制信号。 响应于控制信号，共享移位寄存器块将时钟延迟线和命令延迟线的延迟量设定为彼此基本相同。

    DELAY CONTROL CIRCUIT AND CLOCK GENERATION CIRCUIT INCLUDING THE SAME
    9.
    发明申请
    DELAY CONTROL CIRCUIT AND CLOCK GENERATION CIRCUIT INCLUDING THE SAME 有权
    延迟控制电路和时钟发生电路，包括它们

    公开(公告)号：US20130342250A1

    公开(公告)日：2013-12-26

    申请号：US13711750

    申请日：2012-12-12

    Applicant: SK HYNIX INC.

    Inventor： Dae Han KWON ,  Yong Ju KIM ,  Jae Min JANG ,  Hae Rang CHOI

    IPC: H03L7/085

    CPC classification number: H03L7/085 ,  H03L7/0814 ,  H03L7/0816 ,  H03L7/093 ,  H03L7/095 ,  H03L7/10

    Abstract: A clock generation circuit includes a delay line, which delays an input clock and generates a delayed clock, a delay modeling unit, which delays the delayed clock by a modeled delay value and generates a feedback clock, a phase detection unit, which compares phases of the input clock and the feedback clock and generates a phase detection signal, a filter unit, which receives the phase detection signal and generates phase information, generates an update signal when a difference between the numbers of phase detection signals with a first and a second level generated is greater than or equal to a threshold value, and generates the update signal after a lapse of a predetermined time when the difference is less than the threshold value, and a delay line control unit, which sets a delay value of the delay line in response to the update signal and the phase information.

    Abstract translation: 时钟生成电路包括延迟输入时钟并产生延迟时钟的延迟线，延迟建模单元，其通过建模延迟值延迟延迟时钟并产生反馈时钟，相位检测单元，其比较 输入时钟和反馈时钟，并产生相位检测信号，滤波器单元，其接收相位检测信号并产生相位信息，当相位检测信号的数量与第一和第二电平之间的差异产生更新信号 产生的阈值大于或等于阈值，并且在差小于阈值的经过预定时间之后生成更新信号;以及延迟线控制单元，其将延迟线的延迟值设置在 对更新信号和相位信息的响应。

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