公开(公告)号：US11373898B2

公开(公告)日：2022-06-28

申请号：US16969350

申请日：2019-02-12

Applicant: Soitec

Inventor： Daniel Delprat ,  Damien Parissi ,  Marcel Broekaart

IPC: H01L21/46 ,  H01L23/58 ,  H01L21/762 ,  H01L21/02 ,  H01L21/677

Abstract: A method for manufacturing a semiconductor on insulator type structure by transfer of a layer from a donor substrate onto a receiver substrate, comprises: a) the supply of the donor substrate and the receiver substrate, b) the formation in the donor substrate of an embrittlement zone delimiting the layer to transfer, c) the bonding of the donor substrate on the receiver substrate, the surface of the donor substrate opposite to the embrittlement zone with respect to the layer to transfer being at the bonding interface, and d) the detachment of the donor substrate along the embrittlement zone. A step of controlled modification of the curvature of the donor substrate and/or the receiver substrate is performed before the bonding step.

公开(公告)号：US10943778B2

公开(公告)日：2021-03-09

申请号：US15743004

申请日：2016-07-13

Applicant: Soitec

Inventor： Pascal Guenard ,  Marcel Broekaart ,  Thierry Barge

IPC: H01L21/02 ,  H01L41/312 ,  H01L41/083 ,  H01L41/187 ,  H03H9/02

Abstract: A method for manufacturing a substrate includes the following steps: (a) providing a support substrate with a first coefficient of thermal expansion, having on one of its faces a first plurality of trenches parallel to each other in a first direction, and a second plurality of trenches parallel to each other in a second direction; (b) transferring a useful layer from a donor substrate to the support substrate, the useful layer having a second coefficient of thermal expansion; wherein an intermediate layer is inserted between the front face of the support substrate and the useful layer, the intermediate layer having a coefficient of thermal expansion between the first and second coefficients of thermal expansion.

公开(公告)号：US20200169222A1

公开(公告)日：2020-05-28

申请号：US16614732

申请日：2018-05-23

Applicant: Soitec

Inventor： Marcel Broekaart ,  Frederic Allibert ,  Eric Desbonnets ,  Jean-Pierre Raskin ,  Martin Rack

IPC: H03C7/00 ,  H01L23/66

Abstract: A method for minimizing harmonic distortion and/or intermodulation distortion of a radiofrequency signal propagating in a radiofrequency circuit formed on a semiconductor substrate coated with an electrically insulating layer, wherein a curve representing the distortion as a function of a power of the input or output signal exhibits a trough around a given power (PDip), the method comprises applying, between the radiofrequency circuit and the semiconductor substrate, an electrical potential difference (VGB) chosen so as to move the trough toward a given operating power of the radiofrequency circuit.

公开(公告)号：US20200161172A1

公开(公告)日：2020-05-21

申请号：US16685938

申请日：2019-11-15

Applicant: Soitec

Inventor： Marcel Broekaart ,  Ionut Radu ,  Chrystelle Lagahe Blanchard

IPC: H01L21/762 ,  H01L27/146 ,  H01L23/544

Abstract: The disclosure relates to a process for locating devices, the process comprising the following steps: a) providing a carrier substrate comprising: a device layer; and alignment marks; b) providing a donor substrate; c) forming a weak zone in the donor substrate, the weak zone delimiting a useful layer; d) assembling the donor substrate and the carrier substrate; and e) fracturing the donor substrate in the weak zone so as to transfer the useful layer to the device layer; wherein the alignment marks are placed in cavities formed in the device layer, the cavities having an aperture flush with the free surface of the device layer.

公开(公告)号：US09583531B2

公开(公告)日：2017-02-28

申请号：US14899243

申请日：2014-06-16

Applicant: Soitec

Inventor： Marcel Broekaart ,  Laurent Marinier

IPC: H01L21/00 ,  H01L27/146 ,  H01L21/78 ,  H01L25/00 ,  H01L21/683

CPC classification number: H01L27/14687 ,  H01L21/6835 ,  H01L21/78 ,  H01L25/50 ,  H01L27/14636 ,  H01L27/1464 ,  H01L2221/68363 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A process for transferring a buried circuit layer comprises taking a donor substrate comprising an internal etch stop zone and covered on its front side with a circuit layer, producing over the entire circumference of the donor substrate either a peripheral trench or a peripheral routing, the routing or trench being produced over a depth such that they pass entirely through the circuit layer and extend into the donor substrate, depositing on the circuit layer and on the routed side or on the walls of the trench a layer of an etch stop material that is selective with respect to etching of the circuit layer, without filling the trench, bonding a receiver substrate to the donor substrate, and thinning the donor substrate by etching its back side until reaching the etch stop zone so as to obtain the transfer of the buried circuit layer to the receiver substrate.

Abstract translation: 用于传送掩埋电路层的工艺包括取得包含内部蚀刻停止区的施主衬底，并在其前侧覆盖有电路层，在施主衬底的整个圆周上产生外围沟槽或外围路由，布线 或沟槽在深度上产生，使得它们完全通过电路层并延伸到施主衬底中，在电路层上和在沟道侧或沟槽的壁上沉积有选择性的蚀刻停止材料层 关于电路层的蚀刻，而不填充沟槽，将接收器衬底接合到施主衬底，并且通过蚀刻其背面直到到达蚀刻停止区来稀释施主衬底，以获得掩埋电路层的传输 到接收器基板。

公开(公告)号：US12183624B2

公开(公告)日：2024-12-31

申请号：US17414858

申请日：2020-01-08

Applicant: Soitec

Inventor： Marcel Broekaart ,  Damien Parissi

IPC: H01L21/762 ,  H01L21/02

Abstract: A process for producing a receiver substrate for a semiconductor-on-insulator structure for radiofrequency application comprises the following steps:—providing a semiconductor substrate comprising a base substrate made of monocrystalline material and a charge-trapping layer made of polycrystalline silicon arranged on the base substrate;—oxidizing the charge-trapping layer to form an oxide layer arranged on the charge-trapping layer. The oxidation of the charge-trapping layer is performed at least partly at a temperature lower than or equal to 875° C., in the following manner:—starting the oxidization at a first temperature (T1) between 750° C. and 1000° C.;—decreasing the temperature down to a second temperature (T2), lower than the first temperature (T1), between 750° C. and 875° C.;—continuing the oxidization at the second temperature (T2).

公开(公告)号：US20240014027A1

公开(公告)日：2024-01-11

申请号：US18470975

申请日：2023-09-20

Applicant: Soitec

Inventor： Pascal Guenard ,  Marcel Broekaart ,  Thierry Barge

IPC: H01L21/02 ,  H10N30/50 ,  H10N30/072 ,  H10N30/853

CPC classification number: H01L21/02002 ,  H10N30/50 ,  H10N30/072 ,  H10N30/8542 ,  H01L21/02367 ,  H01L21/02436 ,  H03H9/02574

Abstract: A method for manufacturing a substrate includes the following steps: (a) providing a support substrate with a first coefficient of thermal expansion, having on one of its faces a first plurality of trenches parallel to each other in a first direction, and a second plurality of trenches parallel to each other in a second direction; (b) transferring a useful layer from a donor substrate to the support substrate, the useful layer having a second coefficient of thermal expansion; wherein an intermediate layer is inserted between the front face of the support substrate and the useful layer, the intermediate layer having a coefficient of thermal expansion between the first and second coefficients of thermal expansion.

公开(公告)号：US11373856B2

公开(公告)日：2022-06-28

申请号：US16476415

申请日：2018-01-11

Applicant: Soitec

Inventor： Patrick Reynaud ,  Marcel Broekaart ,  Frederic Allibert ,  Christelle Veytizou ,  Luciana Capello ,  Isabelle Bertrand

IPC: H01L29/66 ,  H01L21/8238 ,  H01L21/02 ,  H01L21/762

Abstract: A support for a semiconductor structure includes a base substrate, a first silicon dioxide insulating layer positioned on the base substrate and having a thickness greater than 20 nm, and a charge trapping layer having a resistivity higher than 1000 ohm·cm and a thickness greater than 5 microns positioned on the first insulating layer.

公开(公告)号：US20210050250A1

公开(公告)日：2021-02-18

申请号：US16969350

申请日：2019-02-12

Applicant: Soitec

Inventor： Daniel Delprat ,  Damien Parissi ,  Marcel Broekaart

IPC: H01L21/762 ,  H01L21/02

Abstract: A method for manufacturing a semiconductor on insulator type structure by transfer of a layer from a donor substrate onto a receiver substrate, comprises: a) the supply of the donor substrate and the receiver substrate, b) the formation in the donor substrate of an embrittlement zone delimiting the layer to transfer, c) the bonding of the donor substrate on the receiver substrate, the surface of the donor substrate opposite to the embrittlement zone with respect to the layer to transfer being at the bonding interface, and d) the detachment of the donor substrate along the embrittlement zone. A step of controlled modification of the curvature of the donor substrate and/or the receiver substrate is performed before the bonding step.

公开(公告)号：US10608610B2

公开(公告)日：2020-03-31

申请号：US16064419

申请日：2016-12-21

Applicant: Soitec

Inventor： Marcel Broekaart ,  Thierry Barge ,  Pascal Guenard ,  Ionut Radu ,  Eric Desbonnets ,  Oleg Kononchuk

IPC: H03H3/10 ,  H03H9/13 ,  H03H9/145 ,  H03H9/17 ,  H03H9/25 ,  H03H9/56 ,  H03H9/64 ,  H01L27/20 ,  H01L41/047 ,  H03H9/02 ,  H01L41/312 ,  H03H3/02 ,  H03H3/04 ,  H01L41/335

Abstract: A substrate for a surface acoustic wave device or bulk acoustic wave device, comprising a support substrate and an piezoelectric layer on the support substrate, wherein the support substrate comprises a semiconductor layer on a stiffening substrate having a coefficient of thermal expansion that is closer to the coefficient of thermal expansion of the material of the piezoelectric layer than that of silicon, the semiconductor layer being arranged between the piezoelectric layer and the stiffening substrate.