公开(公告)号：US09576798B2

公开(公告)日：2017-02-21

申请号：US14934567

申请日：2015-11-06

Applicant: Soitec

Inventor： Bich-Yen Nguyen ,  Walter Schwarzenbach ,  Christophe Maleville

IPC: H01L21/8238 ,  H01L27/12 ,  H01L21/266 ,  H01L21/336 ,  H01L21/225 ,  H01L29/78 ,  H01L21/265 ,  H01L21/02 ,  H01L29/16 ,  H01L29/32 ,  H01L21/84 ,  H01L21/762 ,  H01L29/10

CPC classification number: H01L21/2253 ,  H01L21/0214 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/02532 ,  H01L21/02617 ,  H01L21/26506 ,  H01L21/2652 ,  H01L21/76251 ,  H01L21/76281 ,  H01L21/76283 ,  H01L21/823807 ,  H01L21/823878 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/1054 ,  H01L29/16 ,  H01L29/32 ,  H01L29/7849

Abstract: Methods of fabricating a semiconductor structure include providing a semiconductor-on-insulator (SOI) substrate including a base substrate, a strained stressor layer above the base substrate, a surface semiconductor layer, and a dielectric layer between the stressor layer and the surface semiconductor layer. Ions are implanted into or through a first region of the stressor layer, and additional semiconductor material is formed on the surface semiconductor layer above the first region of the stressor layer. The strain state in the first region of the surface semiconductor layer above the first region of the stressor layer is altered, and a trench structure is formed at least partially into the base substrate. The strain state is altered in a second region of the surface semiconductor layer above the second region of the stressor layer. Semiconductor structures are fabricated using such methods.

Abstract translation: 制造半导体结构的方法包括提供包括基底基板，在基底基板上方的应变应力层，表面半导体层和应力层与表面半导体层之间的电介质层的绝缘体上半导体 。 离子被注入或穿过应力层的第一区域，并且在应力层的第一区域上方的表面半导体层上形成附加的半导体材料。 在应力层的第一区域上方的表面半导体层的第一区域中的应变状态被改变，并且沟槽结构至少部分地形成到基底衬底中。 在应力层的第二区域上方的表面半导体层的第二区域中改变应变状态。 使用这种方法制造半导体结构。

公开(公告)号：US08728913B2

公开(公告)日：2014-05-20

申请号：US13933779

申请日：2013-07-02

Applicant: Soitec

Inventor： Sébastien Kerdiles ,  Walter Schwarzenbach ,  Aziz Alami-Idrissi

IPC: H01L21/30 ,  H01L21/78

CPC classification number: H01L21/30625 ,  H01L21/02032 ,  H01L21/76254

Abstract: The invention relates to a method for transferring a layer from a donor substrate onto a handle substrate wherein, after detachment, the remainder of the donor substrate is reused. To get rid of undesired protruding edge regions that are due to the chamfered geometry of the substrates, the invention proposes to carry out an additional etching process before detachment occurs.

Abstract translation: 本发明涉及一种用于将层从施主衬底转移到手柄衬底上的方法，其中，在剥离之后，再次使用剩余的施主衬底。 为了摆脱由于基板的倒角几何形状引起的不期望的突出边缘区域，本发明提出在拆卸发生之前执行附加的蚀刻工艺。

公开(公告)号：US12261079B2

公开(公告)日：2025-03-25

申请号：US18449298

申请日：2023-08-14

Applicant: Soitec

Inventor： Walter Schwarzenbach ,  Guillaume Chabanne ,  Nicolas Daval

IPC: H01L21/00 ,  H01L21/762

Abstract: A method for fabricating a strained semiconductor-on-insulator substrate comprises bonding a donor substrate to a receiving substrate with a dielectric layer at the interface. The donor substrate comprises a monocrystalline carrier substrate, an intermediate etch-stop layer, and a monocrystalline semiconductor layer. The monocrystalline semiconductor layer is transferred from the donor substrate to the receiving substrate. Trench isolations are formed to cut a portion from a layer stack including the transferred monocrystalline semiconductor layer, the dielectric layer, and the strained semiconductor material layer. The cutting operation results in relaxation of strain in the strained semiconductor material, and in application of strain to the transferred monocrystalline semiconductor layer. After transferring the monocrystalline semiconductor layer and before the cutting operation, a portion of the carrier substrate is selectively etched with respect to the intermediate layer, and the intermediate layer is selectively etched with respect to the monocrystalline semiconductor layer.

公开(公告)号：US12100727B2

公开(公告)日：2024-09-24

申请号：US17418148

申请日：2019-12-23

Applicant: Soitec

Inventor： Walter Schwarzenbach ,  Ludovic Ecarnot ,  Damien Massy ,  Nadia Ben Mohamed ,  Nicolas Daval ,  Christophe Girard ,  Christophe Maleville

IPC: H01L27/146 ,  H01L21/265 ,  H01L21/322 ,  H01L21/762 ,  H01L31/18

CPC classification number: H01L27/14683 ,  H01L21/26506 ,  H01L21/3223 ,  H01L21/3226 ,  H01L21/76254 ,  H01L27/1463 ,  H01L31/1892

Abstract: A method of manufacturing a substrate for a front-facing image sensor, comprises:—providing a donor substrate comprising a semiconductor layer to be transferred,—providing a semiconductor carrier substrate,—bonding the donor substrate to the carrier substrate, an electrically insulating layer being at the bonding interface,—transferring the semiconductor layer to the carrier substrate,—implanting gaseous ions in the carrier substrate via the transferred semiconductor layer and the electrically insulating layer, and—after the implantation, epitaxially growing an additional semiconductor layer on the transferred semiconductor layer.

公开(公告)号：US11876020B2

公开(公告)日：2024-01-16

申请号：US17250767

申请日：2019-09-03

Applicant: Soitec

Inventor： Walter Schwarzenbach ,  Ludovic Ecarnot ,  Nicolas Daval ,  Bich-Yen Nguyen ,  Guillaume Besnard

IPC: H01L21/762 ,  H01L21/8238 ,  H01L21/324

CPC classification number: H01L21/823821 ,  H01L21/3247 ,  H01L21/7624

Abstract: A method for manufacturing a CFET device comprises forming a substrate of the double semi-conductor on insulator type, successively comprising, from the base to the surface thereof: a carrier substrate, a first electrically insulating layer, a first single-crystal semiconductor layer, a second electrically insulating layer and a second single-crystal semiconductor layer. Slices are formed into the substrate to the first electrically insulating layer so as to form at least one fin (F). A channel of a first transistor is formed in the first semiconductor layer and a channel of a second transistor is formed opposite the first transistor in the second semiconductor layer. Formation of the substrate of the double semi-conductor on insulator type comprises: a first and a second step of transferring a layer and thermal processing at a temperature that is sufficiently high to smooth the first single-crystal semiconductor layer to a roughness lower than 0.1 nm RMS.

公开(公告)号：US11728207B2

公开(公告)日：2023-08-15

申请号：US17207202

申请日：2021-03-19

Applicant: Soitec

Inventor： Walter Schwarzenbach ,  Guillaume Chabanne ,  Nicolas Daval

IPC: H01L21/00 ,  H01L21/762

CPC classification number: H01L21/76275 ,  H01L21/76254

Abstract: A method for fabricating a strained semiconductor-on-insulator substrate comprises bonding a donor substrate to a receiving substrate with a dielectric layer at the interface. The donor substrate comprises a monocrystalline carrier substrate, an intermediate etch-stop layer, and a monocrystalline semiconductor layer. The monocrystalline semiconductor layer is transferred from the donor substrate to the receiving substrate. Trench isolations are formed to cut a portion from a layer stack including the transferred monocrystalline semiconductor layer, the dielectric layer, and the strained semiconductor material layer. The cutting operation results in relaxation of strain in the strained semiconductor material, and in application of strain to the transferred monocrystalline semiconductor layer. After transferring the monocrystalline semiconductor layer and before the cutting operation, a portion of the carrier substrate is selectively etched with respect to the intermediate layer, and the intermediate layer is selectively etched with respect to the monocrystalline semiconductor layer.

公开(公告)号：US11476153B2

公开(公告)日：2022-10-18

申请号：US17276107

申请日：2019-09-11

Applicant: Soitec

Inventor： Walter Schwarzenbach

IPC: H01L21/762 ,  H01L27/12 ,  H01L21/84 ,  H01L21/02

Abstract: A method of forming a substrate comprises providing a receiver substrate and a donor substrate successively comprising: a carrier substrate, a sacrificial layer, which can be selectively etched in relation to an active layer, and a silicon oxide layer, which is arranged on the active layer. A cavity is formed in the oxide layer to form a first portion that has a first thickness and a second portion that has a second thickness greater than the first thickness. The cavity is filled with a polycrystalline silicon filling layer to form a second free surface that is continuous and substantially planar. The receiver substrate and the donor substrate are assembled at the second free surface, and the carrier substrate is eliminated while preserving the active layer and the sacrificial layer.

公开(公告)号：US11127775B2

公开(公告)日：2021-09-21

申请号：US16477374

申请日：2018-01-10

Applicant: Soitec

Inventor： Walter Schwarzenbach ,  Oleg Kononchuk ,  Ludovic Ecarnot ,  Christelle Michau

IPC: H01L27/146 ,  H01L27/12

Abstract: A substrate for a front-side-type image sensor includes, successively, a supporting semiconductor substrate, an electrically insulating layer, and a semiconductor layer, known as the active layer. The active layer is an epitaxial layer of silicon-germanium having a germanium content of less than 10%. The disclosure also relates to a method for the production of such a substrate.

公开(公告)号：US20210225695A1

公开(公告)日：2021-07-22

申请号：US17207202

申请日：2021-03-19

Applicant: Soitec

Inventor： Walter Schwarzenbach ,  Guillaume Chabanne ,  Nicolas Daval

IPC: H01L21/762

Abstract: A method for fabricating a strained semiconductor-on-insulator substrate comprises bonding a donor substrate to a receiving substrate with a dielectric layer at the interface. The donor substrate comprises a monocrystalline carrier substrate, an intermediate etch-stop layer, and a monocrystalline semiconductor layer. The monocrystalline semiconductor layer is transferred from the donor substrate to the receiving substrate. Trench isolations are formed to cut a portion from a layer stack including the transferred monocrystalline semiconductor layer, the dielectric layer, and the strained semiconductor material layer. The cutting operation results in relaxation of strain in the strained semiconductor material, and in application of strain to the transferred monocrystalline semiconductor layer. After transferring the monocrystalline semiconductor layer and before the cutting operation, a portion of the carrier substrate is selectively etched with respect to the intermediate layer, and the intermediate layer is selectively etched with respect to the monocrystalline semiconductor layer.

公开(公告)号：US20210202326A1

公开(公告)日：2021-07-01

申请号：US17250767

申请日：2019-09-03

Applicant: Soitec

Inventor： Walter Schwarzenbach ,  Ludovic Ecarnot ,  Nicolas Daval ,  Bich-Yen Nguyen ,  Guillaume Besnard

IPC: H01L21/8238 ,  H01L21/762 ,  H01L21/324

Abstract: A method for manufacturing a CFET device comprises forming a substrate of the double semi-conductor on insulator type, successively comprising, from the base to the surface thereof: a carrier substrate, a first electrically insulating layer, a first single-crystal semiconductor layer, a second electrically insulating layer and a second single-crystal semiconductor layer. Slices are formed into the substrate to the first electrically insulating layer so as to form at least one fin (F). A channel of a first transistor is formed in the first semiconductor layer and a channel of a second transistor is formed opposite the first transistor in the second semiconductor layer. Formation of the substrate of the double semi-conductor on insulator type, comprises: a first and a second step of transferring a layer and thermal processing at a temperature that is sufficiently high to smooth the first single-crystal semiconductor layer to a roughness lower than 0.1 nm RMS.