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公开(公告)号：US11675943B2
公开(公告)日：2023-06-13
申请号：US17094743
申请日：2020-11-10
发明人： Thomas Boesch , Giuseppe Desoli
IPC分类号： G06F30/327 , G06N20/10 , G06N3/084 , G06F30/34 , G06N20/00 , G06N3/044 , G06N3/045 , G06N3/047 , G06N3/04 , G06N3/08 , G06F115/08 , G06N7/01 , G06N3/063 , G06F9/445 , G06F13/40 , G06F15/78
CPC分类号： G06F30/327 , G06F30/34 , G06N3/044 , G06N3/045 , G06N3/047 , G06N3/084 , G06N20/00 , G06N20/10 , G06F9/44505 , G06F13/4022 , G06F15/7817 , G06F2115/08 , G06N3/04 , G06N3/063 , G06N3/08 , G06N7/01
摘要： Embodiments are directed towards a method to create a reconfigurable interconnect framework in an integrated circuit. The method includes accessing a configuration template directed toward the reconfigurable interconnect framework, editing parameters of the configuration template, functionally combining the configuration template with a plurality of modules from an IP library to produce a register transfer level (RTL) circuit model, generating at least one automated test-bench function, and generating at least one logic synthesis script. Editing parameters of the configuration template includes confirming a first number of output ports of a reconfigurable stream switch and confirming a second number of input ports of the reconfigurable stream switch. Each output port and each input port has a respective architectural composition. The output port architectural composition is defined by a plurality of N data paths including A data outputs and B control outputs. The input port architectural composition is defined by a plurality of M data paths including A data inputs and B control inputs.
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公开(公告)号：US11360667B2
公开(公告)日：2022-06-14
申请号：US17012501
申请日：2020-09-04
发明人： Nitin Chawla , Giuseppe Desoli , Anuj Grover , Thomas Boesch , Surinder Pal Singh , Manuj Ayodhyawasi
摘要： A memory array arranged as a plurality of memory cells. The memory cells are configured to operate at a determined voltage. A memory management circuitry coupled to the plurality of memory cells tags a first set of the plurality of memory cells as low-voltage cells and tags a second set of the plurality of memory cells as high-voltage cells. A power source provides a low voltage to the first set of memory cells and provides a high voltage to the second set of memory cells based on the tags.
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公开(公告)号：US10726177B2
公开(公告)日：2020-07-28
申请号：US16517371
申请日：2019-07-19
发明人： Thomas Boesch , Giuseppe Desoli
IPC分类号： G06F9/455 , G06F13/42 , G06F30/327 , G06N3/04 , G06N3/08 , G06F30/34 , G06N3/063 , G06F9/445 , G06F13/40 , G06F15/78 , G06N20/10 , G06N7/00 , G06F115/08
摘要： A system on a chip (SoC) includes a plurality of processing cores and a stream switch coupled to two or more of the plurality of processing cores. The stream switch includes a plurality of N multibit input ports, wherein N is a first integer. a plurality of M multibit output ports, wherein M is a second integer, and a plurality of M multibit stream links dedicated to respective output ports of the plurality of M multibit output ports. The M multibit stream links are reconfigurably coupleable at run time to a selectable number of the N multibit input ports, wherein the selectable number is an integer between zero and N.
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公开(公告)号：US11977971B2
公开(公告)日：2024-05-07
申请号：US18167366
申请日：2023-02-10
IPC分类号： G06T7/62 , G06F9/38 , G06F16/901 , G06F18/22 , G06N3/045 , G06N3/063 , G06N3/08 , G06T7/11 , G06T15/08 , G06V10/82 , G06V20/00 , G06V10/75
CPC分类号： G06N3/063 , G06F9/3877 , G06F16/9024 , G06F18/22 , G06N3/045 , G06N3/08 , G06T7/11 , G06T7/62 , G06T15/08 , G06V10/82 , G06V20/00 , G06V10/759
摘要： A device include on-board memory, an applications processor, a digital signal processor (DSP) cluster, a configurable accelerator framework (CAF), and a communication bus architecture. The communication bus communicatively couples the applications processor, the DSP cluster, and the CAF to the on-board memory. The CAF includes a reconfigurable stream switch and data volume sculpting circuitry, which has an input and an output coupled to the reconfigurable stream switch. The data volume sculpting circuitry receives a series of frames, each frame formed as a two dimensional (2D) data structure, and determines a first dimension and a second dimension of each frame of the series of frames. Based on the first and second dimensions, the data volume sculpting circuitry determines for each frame a position and a size of a region-of-interest to be extracted from the respective frame, and extracts from each frame, data in the frame that is within the region-of-interest.
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公开(公告)号：US11880759B2
公开(公告)日：2024-01-23
申请号：US18172979
申请日：2023-02-22
CPC分类号： G06N3/045 , G06F16/2282 , G06F18/217 , G06N3/04 , G06N3/063 , G06N3/08
摘要： Embodiments of an electronic device include an integrated circuit, a reconfigurable stream switch formed in the integrated circuit along with a plurality of convolution accelerators and a decompression unit coupled to the reconfigurable stream switch. The decompression unit decompresses encoded kernel data in real time during operation of convolutional neural network.
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公开(公告)号：US11740870B2
公开(公告)日：2023-08-29
申请号：US16833353
申请日：2020-03-27
CPC分类号： G06F7/5443 , G06N3/04
摘要： A Multiple Accumulate (MAC) hardware accelerator includes a plurality of multipliers. The plurality of multipliers multiply a digit-serial input having a plurality of digits by a parallel input having a plurality of bits by sequentially multiplying individual digits of the digit-serial input by the plurality of bits of the parallel input. A result is generated based on the multiplication of the digit-serial input by the parallel input. An accelerator framework may include multiple MAC hardware accelerators, and may be used to implement a convolutional neural network. The MAC hardware accelerators may multiple an input weight by an input feature by sequentially multiplying individual digits of the input weight by the input feature.
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公开(公告)号：US11726543B2
公开(公告)日：2023-08-15
申请号：US17111373
申请日：2020-12-03
发明人： Nitin Chawla , Anuj Grover , Giuseppe Desoli , Kedar Janardan Dhori , Thomas Boesch , Promod Kumar
IPC分类号： G06F1/3234 , G05F3/24 , G06F1/3287 , G06F15/78 , G11C11/413 , G11C5/14 , G11C11/417 , G06F1/26
CPC分类号： G06F1/3275 , G05F3/24 , G06F1/3287 , G06F15/7821 , G11C11/413
摘要： Systems and devices are provided to enable granular control over a retention or active state of each of a plurality of memory circuits, such as a plurality of memory cell arrays, within a memory. Each respective memory array of the plurality of memory arrays is coupled to a respective ballast driver and a respective active memory signal switch for the respective memory array. One or more voltage regulators are coupled to a ballast driver gate node and to a bias node of at least one of the respective memory arrays. In operation, the respective active memory signal switch for a respective memory array causes the respective memory array to transition between an active state for the respective memory array and a retention state for the respective memory array.
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公开(公告)号：US11610362B2
公开(公告)日：2023-03-21
申请号：US17194055
申请日：2021-03-05
IPC分类号： G06T7/62 , G06T7/11 , G06T15/08 , G06F16/901 , G06F9/38 , G06K9/62 , G06N3/08 , G06N3/04 , G06N3/063 , G06V20/00 , G06V10/82 , G06V10/75
摘要： A device include on-board memory, an applications processor, a digital signal processor (DSP) cluster, a configurable accelerator framework (CAF), and at least one communication bus architecture. The communication bus communicatively couples the applications processor, the DSP cluster, and the CAF to the on-board memory. The CAF includes a reconfigurable stream switch and data volume sculpting circuitry, which has an input and an output coupled to the reconfigurable stream switch. The data volume sculpting circuitry receives a series of frames, each frame formed as a two dimensional (2D) data structure, and determines a first dimension and a second dimension of each frame of the series of frames. Based on the first and second dimensions, the data volume sculpting circuitry determines for each frame a position and a size of a region-of-interest to be extracted from the respective frame, and extracts from each frame, data in the frame that is within the region-of-interest.
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公开(公告)号：US11836346B2
公开(公告)日：2023-12-05
申请号：US17742987
申请日：2022-05-12
发明人： Nitin Chawla , Giuseppe Desoli , Anuj Grover , Thomas Boesch , Surinder Pal Singh , Manuj Ayodhyawasi
CPC分类号： G06F3/0604 , G06F3/0619 , G06F3/0655 , G06F3/0679 , G06N3/08
摘要： A memory array arranged as a plurality of memory cells. The memory cells are configured to operate at a determined voltage. A memory management circuitry coupled to the plurality of memory cells tags a first set of the plurality of memory cells as low-voltage cells and tags a second set of the plurality of memory cells as high-voltage cells. A power source provides a low voltage to the first set of memory cells and provides a high voltage to the second set of memory cells based on the tags.
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公开(公告)号：US11823771B2
公开(公告)日：2023-11-21
申请号：US17158875
申请日：2021-01-26
摘要： A system includes a random access memory organized into individually addressable words. Streaming access control circuitry is coupled to word lines of the random access memory. The streaming access control circuitry responds to a request to access a plurality of individually addressable words of a determined region of the random access memory by generating control signals to drive the word lines to streamingly access the plurality of individually addressable words of the determined region. The request indicates an offset associated with the determined region and a pattern associated with the streaming access.
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