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公开(公告)号：US08990436B2
公开(公告)日：2015-03-24
申请号：US13904379
申请日：2013-05-29
Applicant: STMicroelectronics S.r.l.
Inventor： Daniele Mangano , Salvatore Pisasale , Mirko Dondini
CPC classification number: G06F9/466 , G06F13/1626 , G06F2213/0038
Abstract: In an embodiment, access transactions of at least one module of a system such as a System-on-Chip (SoC) to one of a plurality of target modules, such as memories, are managed by assigning transactions identifiers subjected to a consistency check. If an input identifier to the check has already been issued for the same given target module, to the related identifier/given target module pair the same input identifier is assigned as a consistent output identifier. If, on the contrary, said input identifier to the check has not been already issued or has already been issued for a target module different from the considered one, to the related identifier/given target module pair a new identifier, different from the input identifier, is assigned as a consistent output identifier.
Abstract translation: 在一个实施例中，通过分配经过一致性检查的事务标识符来管理诸如片上系统（SoC）的系统的至少一个模块到诸如存储器的多个目标模块之一的访问事务。 如果已经为相同的给定目标模块发出了支票的输入标识符，则向相关标识符/给定目标模块对发送相同的输入标识符作为一致的输出标识符。 相反，如果相对于所述检查的所述输入标识符尚未被发布或者已经针对与所考虑的目标模块不同的目标模块已经被发布到相关标识符/给定目标模块对，则与输入标识符不同的新标识符 ，被分配为一致的输出标识符。
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12.发明申请METHOD AND SYSTEM FOR PERFORMING DIVISION/MULTIPLICATION OPERATIONS IN DIGITAL PROCESSORS, CORRESPONDING DEVICE AND COMPUTER PROGRAM PRODUCT 审中-公开在数字处理器，对应设备和计算机程序产品中执行部门/多媒体操作的方法和系统公开(公告)号：US20140379769A1
公开(公告)日：2014-12-25
申请号：US14313273
申请日：2014-06-24
Applicant: STMicroelectronics S.r.l.
Inventor： Daniele Mangano
IPC: G06F5/01
Abstract: A digital processor, such as, e.g., a divider in a PID controller, performs a mathematical operation such as division (or multiplication) involving operands represented by strings of bit signals and an operator to produce an operation result. The processor is configured by identifying first and second power-of-two approximating values of the operator as the nearest lower and nearest higher power-of-two values to the operator. The operation is performed on the input operands by means of the first and second power-of-two approximating values of the operator by shifting the bit signals in the operands by using the first and second power-of-two approximating values in an alternated sequence to produce: first approximate results by using the first power-of-two approximating value, second approximate results by using the second power-of-two approximating value. The average of the first and second approximate results is representative of the accurate result of the operation.
Abstract translation: 数字处理器，例如PID控制器中的分频器，执行数学运算，例如涉及由位信号串和运算符表示的操作数的除法（或乘法）以产生运算结果。 通过将操作者的第一和第二二次近似值识别为操作者的最接近的较低和最接近的较高功率值来配置处理器。 通过使用操作数中的位信号通过使用交替序列中的第一和第二二次近似值来通过操作者的第一和第二二次近似值对输入操作数执行操作 产生：通过使用第二二次近似值的第一近似结果，通过使用第二二次幂近似值的第二近似结果。 第一和第二近似结果的平均值代表操作的准确结果。
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13.发明申请BUFFER FOR ORDERING OUT-OF-ORDER DATA, AND CORRESPONDING INTEGRATED CIRCUIT AND METHOD FOR MANAGING A BUFFER 有权用于订购不合规格数据的缓冲器，以及相关的集成电路和用于管理缓冲器的方法公开(公告)号：US20140185390A1
公开(公告)日：2014-07-03
申请号：US14143383
申请日：2013-12-30
Applicant: STMicroelectronics S.r.l.
Inventor： Daniele Mangano , Salvatore Marco Rosselli , Giuseppe Falconeri
IPC: G11C7/10
CPC classification number: G11C7/1006 , G06F5/10 , G06F2205/106 , G06F2205/123
Abstract: A buffer for ordering out-of-order data includes a memory with a plurality of memory locations for temporarily storing data and a detection circuit configured for generating a control signal when the memory locations contain valid data. The detection circuit includes a first block configured for generating validity signals that identify the memory locations containing valid data and a search circuit configured for determining a search pointer as a function of the validity signals. In the case where each memory location contains valid data, the search pointer indicates the last memory location. In the case where at least one memory location is still free, the search pointer indicates the first memory location that is free.
Abstract translation: 用于排序无序数据的缓冲器包括具有用于临时存储数据的多个存储器位置的存储器和被配置为当存储器位置包含有效数据时生成控制信号的检测电路。 检测电路包括被配置用于产生识别包含有效数据的存储位置的有效信号的第一块和被配置为根据有效信号确定搜索指针的搜索电路。 在每个存储器位置包含有效数据的情况下，搜索指针指示最后的存储器位置。 在至少一个存储器位置仍然空闲的情况下，搜索指针指示第一存储器位置是空闲的。
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公开(公告)号：US11764731B2
公开(公告)日：2023-09-19
申请号：US18059812
申请日：2022-11-29
Applicant: STMicroelectronics (Alps) SAS , STMicroelectronics (Grenoble 2) SAS , STMicroelectronics (Rousset) SAS , STMicroelectronics S.r.l.
CPC classification number: H03B5/36 , G06F1/10 , H03F3/245 , H04B1/0475 , H03B2200/004 , H03F2200/451 , H04B2001/0408
Abstract: The present disclosure relates to an electronic device comprising a first capacitor and a quartz crystal coupled in series between a first node and a second node; an inverter coupled between the first and second nodes; a first variable capacitor coupled between the first node and a third node; and a second variable capacitor coupled between the second node and the third node.
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公开(公告)号：US11644504B2
公开(公告)日：2023-05-09
申请号：US16791020
申请日：2020-02-14
Applicant: STMicroelectronics S.r.l.
Inventor： Mirko Dondini , Daniele Mangano , Salvatore Pisasale
IPC: G01R31/3185 , G01R29/027 , G01R31/319 , G06F1/08 , G06F1/12 , G06F13/24
CPC classification number: G01R31/318552 , G01R29/0273 , G01R31/31922 , G01R31/318594 , G06F1/08 , G06F1/12 , G06F13/24
Abstract: In accordance with an embodiment, a system includes an oscillator equipped circuit having an oscillator control circuit configured to be coupled to an external oscillator and a processing unit comprising a clock controller. The clock controller includes an interface circuit configured to exchange handshake signals with the oscillator control circuit, a security circuit configured to receive the external oscillator clock signal and configured to select the external oscillator clock signal as the system clock, and a detection block configured to detect a failure in the external oscillator clock signal. Upon detection of the failure, a different clock signal is selected as the system clock and the interface circuit to interrupts a propagation of the external oscillator.
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Patent Agency Ranking
公开(公告)号：US11239796B2
公开(公告)日：2022-02-01
申请号：US17180748
申请日：2021-02-20
Abstract: An embodiment of the present disclosure relates to a device comprising an electronic circuit; an oscillation circuit comprising a quartz crystal, configured to provide a clock signal to the electronic circuit; and a heater configured to increase the temperature of the quartz crystal.
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公开(公告)号：US20190354152A1
公开(公告)日：2019-11-21
申请号：US16405086
申请日：2019-05-07
Applicant: STMicroelectronics S.r.l.
Inventor： Daniele Mangano , Gaetano Di Stefano , Mirko Dondini
IPC: G06F1/24 , G06F11/267 , H03K3/037
Abstract: A circuit includes a first node configured to receive a reset signal. A reset drive stage drives a reset node. The reset drive stage is coupled to the first node via a reset signal path to propagate the reset signal to the reset drive stage. The reset drive stage is activated as a result of assertion of a reset actuation state of the reset signal. A sensing node is coupled to the reset node via a signal sensing path. The sensing node is sensitive to a signal level of the reset node reaching a reset threshold. A reset signal hold circuit block is coupled to the first node and is configured to receive a reset command signal and assert the reset actuation state of the reset signal at the first node as a result of the reset command signal received.
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公开(公告)号：US20190107597A1
公开(公告)日：2019-04-11
申请号：US16213534
申请日：2018-12-07
Applicant: STMicroelectronics S.r.l.
Inventor： Riccardo Condorelli , Daniele Mangano
CPC classification number: G01R35/005 , G01D3/028 , G01D5/24 , G01R27/02 , G01R27/2605 , G01R35/00 , H02J7/045 , H02J7/345
Abstract: A method of interfacing a LC sensor with a control unit is provided. The control unit may include first and second contacts, where the LC sensor is connected between the first and the second contact. A capacitor is connected between the first contact and a ground. To start the oscillation of the LC sensor, the method may include during a first phase, connecting the first contact to a supply voltage and placing the second contact in a high impedance state such that the capacitor is charged through the supply voltage. During a second phase, the first contact may be placed in a high impedance state, and the second contact connected to the ground such that the capacitor transfers charge towards the LC sensor. During a third phase, the first contact and the second contact may be placed in a high impedance state so the LC sensor is able to oscillate.
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公开(公告)号：US10088333B2
公开(公告)日：2018-10-02
申请号：US14444920
申请日：2014-07-28
Applicant: STMicroelectronics S.r.l.
Inventor： Daniele Mangano
IPC: G01D18/00 , G01D21/00 , G01P21/00 , G01R35/00 , G01C25/00 , G01C19/00 , G01C21/10 , G01C21/18 , G01C21/12 , G01C21/16
Abstract: A method for real-time calibration of a gyroscope, configured for supplying a value of angular velocity that is function of a first angle of rotation about a first angular-sensing axis that includes defining a time interval, acquiring from an accelerometer an equivalent value of angular velocity that can be associated to the first angle of rotation; calculating a deviation between the value of angular velocity and the equivalent value of angular velocity; iteratively repeating the previous steps through the time interval, incrementing or decrementing an offset variable by a first predefined value on the basis of the values assumed by the deviations during the iterations, and updating the value of angular velocity as a function of the offset variable.
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公开(公告)号：US09990329B2
公开(公告)日：2018-06-05
申请号：US14969642
申请日：2015-12-15
Applicant: STMICROELECTRONICS S.R.L.
Inventor： Daniele Mangano , Riccardo Condorelli , Gaetano Distefano
CPC classification number: G06F13/4282 , G06F13/4027 , G06F13/4291
Abstract: A method that is for operating a serial protocol interface includes a communication device that is configured to exchange data over a communication link by sending output data on the communication link, and receiving input data on the communication link. The input data is synchronous with a clock signal generated at the communication device and propagated over the communication link. The method also includes initializing operation by sending the output data on the communication link at a first data rate, detecting a signal transition in the input data received on the communication link, and exchanging data over the communication link at a second data rate when the signal transition is detected, the second data rate being higher than the first data, with the exchanging of data at the second data rate synchronized as a function of the signal transition.
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