公开(公告)号：US09870947B1

公开(公告)日：2018-01-16

申请号：US15632878

申请日：2017-06-26

Applicant: STMicroelectronics (Grenoble 2) SAS ,  STMicroelectronics SA ,  Commissariat A L'Energie Atomique et aux Energies Alternatives

Inventor： Didier Campos ,  Benoit Besancon ,  Perceval Coudrain ,  Jean-Philippe Colonna

IPC: H01L23/29 ,  H01L21/78 ,  H01L21/56 ,  H01L23/373 ,  H01L23/00 ,  H01L21/782 ,  H01L21/683

CPC classification number: H01L21/78 ,  H01L21/56 ,  H01L21/6836 ,  H01L21/782 ,  H01L23/29 ,  H01L23/36 ,  H01L23/373 ,  H01L23/562 ,  H01L2224/16225 ,  H01L2224/73204 ,  H01L2224/97 ,  H01L2924/15174 ,  H01L2924/15311 ,  H01L2924/18161

Abstract: Electronic devices are manufactured using a collective (wafer-scale) fabrication process. Electronic chips are mounted onto one face of a collective substrate wafer. A collective flexible sheet made of a heat-conductive material comprising a layer containing pyrolytic graphite is fixed to extend over a collective region extending over the electronic chips and over the collective substrate wafer between the electronic chips. The collective flexible sheet is then compressed. A dicing operation is then carried out in order to obtain electronic devices each including an electronic chip, a portion of the collective plate and a portion of the collective flexible sheet.

公开(公告)号：US20170127567A1

公开(公告)日：2017-05-04

申请号：US15131652

申请日：2016-04-18

Applicant: STMicroelectronics (Grenoble 2) SAS

Inventor： Benoit Besancon ,  Agnes Baffert ,  Karine Saxod

IPC: H05K7/20 ,  H05K1/02 ,  H05K1/18

CPC classification number: H05K7/20509 ,  H01L23/3128 ,  H01L23/4334 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/19107 ,  H05K1/0203 ,  H05K1/181 ,  H05K2201/066 ,  H05K2201/10734 ,  H01L2924/00012 ,  H01L2924/00014 ,  H01L2924/00

Abstract: An electronic device includes a support plate with an integrated circuit chip fixed onto the support plate. A heat sink is mounted to the support plate. An electrical connection wire is provided with one end electrically connected to the heat sink and another end electrically connected to an electrical contact provided on the support plate.

公开(公告)号：US10833208B2

公开(公告)日：2020-11-10

申请号：US16581978

申请日：2019-09-25

Applicant: STMicroelectronics (Grenoble 2) SAS

Inventor： Karine Saxod ,  Alexandre Mas ,  Eric Saugier ,  Gaetan Lobascio ,  Benoit Besancon

IPC: H01L31/0203 ,  H01L31/0232 ,  H01L31/18 ,  H01L31/02 ,  H01L31/12 ,  B29C45/14 ,  H01L33/48 ,  B29L31/34

Abstract: A cover for an electronic package is manufactured by placing an optical insert, having opposite faces and configured to allow light radiation to pass therethrough, between two opposite faces of a cavity of a mold in a position such that said optical faces of the optical insert make contact with said opposite faces of the cavity of the mold. A coating material is injected into the cavity and around the optical insert. The coating material is set to obtain a substrate that is overmolded around the optical insert so as to produce the cover. An electronic package includes an electronic chip mounted to a support substrate with the cover formed by the overmolded substrate mounted to the support substrate.

公开(公告)号：US10325784B2

公开(公告)日：2019-06-18

申请号：US15685552

申请日：2017-08-24

Applicant: STMicroelectronics (Grenoble 2) SAS

Inventor： Benoit Besancon ,  Alexandre Mas ,  Karine Saxod

IPC: H01L21/56 ,  H01L23/31 ,  H01L23/552 ,  H01L23/053 ,  H01L23/06 ,  H01L23/10 ,  H01L23/24 ,  H01L23/42 ,  H01L23/433 ,  H01L21/52 ,  H01L23/04 ,  H01L21/48

Abstract: A method for manufacturing a cover for an electronic package includes placing an insert having opposite faces between opposite faces of a cavity of a mold. A coating material is injected in the mold cavity around the insert. The coating material is then set to form a substrate that is overmolded around the insert and produce the cover.

公开(公告)号：US20180005889A1

公开(公告)日：2018-01-04

申请号：US15632878

申请日：2017-06-26

Applicant: STMicroelectronics (Grenoble 2) SAS ,  STMicroelectronics SA ,  Commissariat A L'Energie Atomique et aux Energies Alternatives

Inventor： Didier Campos ,  Benoit Besancon ,  Perceval Coudrain ,  Jean-Philippe Colonna

IPC: H01L21/78 ,  H01L23/373 ,  H01L23/00 ,  H01L21/56 ,  H01L21/683 ,  H01L23/29 ,  H01L21/782

CPC classification number: H01L21/78 ,  H01L21/56 ,  H01L21/6836 ,  H01L21/782 ,  H01L23/29 ,  H01L23/36 ,  H01L23/373 ,  H01L23/562 ,  H01L2224/16225 ,  H01L2224/73204 ,  H01L2224/97 ,  H01L2924/15174 ,  H01L2924/15311 ,  H01L2924/18161

Abstract: Electronic devices are manufactured using a collective (wafer-scale) fabrication process. Electronic chips are mounted onto one face of a collective substrate wafer. A collective flexible sheet made of a heat-conductive material comprising a layer containing pyrolytic graphite is fixed to extend over a collective region extending over the electronic chips and over the collective substrate wafer between the electronic chips. The collective flexible sheet is then compressed. A dicing operation is then carried out in order to obtain electronic devices each including an electronic chip, a portion of the collective plate and a portion of the collective flexible sheet.

公开(公告)号：US20170345805A1

公开(公告)日：2017-11-30

申请号：US15166726

申请日：2016-05-27

Applicant: STMicroelectronics (Grenoble 2) SAS

Inventor： Norbert Chevrier ,  Benoit Besancon ,  Jean-Michel Riviere

IPC: H01L25/16 ,  H01L25/00 ,  H01L23/522 ,  H01L21/768 ,  H01L23/31 ,  H01L23/29 ,  H01L27/02 ,  H01L23/00

CPC classification number: H01L25/16 ,  H01L21/76804 ,  H01L21/76879 ,  H01L23/3135 ,  H01L23/5226 ,  H01L23/60 ,  H01L24/16 ,  H01L25/50 ,  H01L27/0251 ,  H01L2224/16227 ,  H01L2224/48227 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/1533 ,  H01L2924/15331

Abstract: Disclosed herein is an electronic device including a substrate having a conductive area formed thereon. A first molding level is stacked on the substrate. A die is formed on the substrate and within the first molding level. A second molding level is stacked on the first molding level. At least one passive component is within the second molding level. A conductive structure extends between the second molding level and the substrate and electrically couples the at least one passive component to the conductive area.

公开(公告)号：US09818664B2

公开(公告)日：2017-11-14

申请号：US15240482

申请日：2016-08-18

Applicant: STMicroelectronics (Grenoble 2) SAS

Inventor： Benoit Besancon ,  Luc Petit

IPC: H01L23/02 ,  H01L29/40 ,  H01L23/31 ,  H01L23/498 ,  H01L21/56 ,  H01L21/78 ,  H01L23/00

CPC classification number: H01L23/3128 ,  H01L21/561 ,  H01L21/565 ,  H01L21/78 ,  H01L23/49838 ,  H01L23/562 ,  H01L24/17 ,  H01L24/81 ,  H01L24/97 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/97 ,  H01L2924/15311 ,  H01L2924/1815 ,  H01L2924/351 ,  H01L2224/81

Abstract: An electronic device includes a carrier substrate with at least one electronic-circuit chip mounted on a front face of the carrier substrate. An encapsulation block on the front face and embedding the electronic-circuit chip has a periphery with corners. The encapsulating block further has, in at least one local zone located in at least one corner and from the front face of the carrier substrate, a smaller thickness than a thickness of the encapsulation block at least in a surrounding zone. The electronic device is manufactured by a process in which the zone of smaller thickness is obtained by molding or by machining.