公开(公告)号：US09753665B2

公开(公告)日：2017-09-05

申请号：US15053950

申请日：2016-02-25

Applicant: STMicroelectronics (Rousset) SAS

Inventor： François Tailliet ,  Marc Battista

IPC: G06F3/06

CPC classification number: G06F3/0634 ,  G06F3/0604 ,  G06F3/0644 ,  G06F3/0688 ,  G11C5/066 ,  G11C7/10 ,  G11C8/12

Abstract: A memory device includes an input/output interface, a bus of SPI type coupled to the input/output interface, and a plurality of individual non-volatile memory devices connected to the bus of SPI type. The chip select inputs of each individual memory device are all connected to one and the same chip select wire of the SPI bus. The individual memory devices are further configured and controllable so as to behave, as seen by the input/output interface, as a single non-volatile memory device, the total memory space of which has a total memory capacity equal to the sum of the individual memory capacities of the individual devices.

公开(公告)号：US20170092357A1

公开(公告)日：2017-03-30

申请号：US15054015

申请日：2016-02-25

Applicant: STMicroelectronics (Rousset) SAS

Inventor： François Tailliet ,  Marc Battista

IPC: G11C13/00

CPC classification number: G11C13/0097 ,  G11C5/144 ,  G11C13/0069 ,  G11C16/10 ,  G11C16/14 ,  G11C16/30 ,  G11C16/32 ,  G11C16/3418 ,  G11C29/12005

Abstract: A method of controlling a cycle for writing at least one data item to at least one memory slot of the electrically programmable and erasable read-only memory type disposed in an electronic circuit supplied by a supply voltage includes a controlled increase of the duration of the write cycle in the presence of a decrease in the supply voltage.

公开(公告)号：US20130278330A1

公开(公告)日：2013-10-24

申请号：US13868866

申请日：2013-04-23

Applicant: STMICROELECTRONICS (ROUSSET) SAS

Inventor： Francois Tailliet ,  Marc Battista

IPC: H03H11/04

CPC classification number: H03H11/04 ,  H03K5/1252 ,  H03K5/13 ,  H03K2005/00156

Abstract: A low pass filter comprises a filter input node configured to receive a first logic signal, a filter output node configured to supply a second logic signal, a resistive element comprising a first terminal coupled to the input node and a second terminal coupled to the output node, and a capacitive element comprising a first terminal coupled to the output node and a second terminal. The filter further comprises an inverting gate having a first terminal coupled to the input node and a second terminal coupled to the second terminal of the capacitive element.

Abstract translation: 低通滤波器包括被配置为接收第一逻辑信号的滤波器输入节点，被配置为提供第二逻辑信号的滤波器输出节点，包括耦合到输入节点的第一终端的电阻元件和耦合到输出节点的第二终端 以及电容元件，包括耦合到所述输出节点的第一端子和第二端子。 滤波器还包括反相门，其具有耦合到输入节点的第一端子和耦合到电容元件的第二端子的第二端子。

公开(公告)号：US11817149B2

公开(公告)日：2023-11-14

申请号：US17930250

申请日：2022-09-07

Applicant: STMicroelectronics (Rousset) SAS

Inventor： François Tailliet ,  Marc Battista

IPC: G11C16/04 ,  G11C14/00

CPC classification number: G11C14/0063

Abstract: An integrated circuit comprises a memory device including at least one memory point having a volatile memory cell and a single non-volatile memory cell coupled together to a common node.

公开(公告)号：US11386963B2

公开(公告)日：2022-07-12

申请号：US17166107

申请日：2021-02-03

Applicant: STMicroelectronics (Rousset) SAS

Inventor： François Tailliet ,  Marc Battista

IPC: G11C16/04 ,  G11C16/14 ,  G11C16/26 ,  G11C16/30

Abstract: The memory device of the electrically-erasable programmable read-only memory type comprises write circuitry designed to carry out a write operation in response to receiving a command for writing at least one selected byte in at least one selected memory word of the memory plane, the write operation comprising an erase cycle followed by a programming cycle, and configured for generating, during the erase cycle, an erase voltage in the memory cells of all the bytes of the at least one selected memory word, and an erase inhibit potential configured, with respect to the erase voltage, for preventing the erasing of the memory cells of the non-selected bytes of the at least one selected memory word, which are not the at least one selected byte.

公开(公告)号：US11120878B2

公开(公告)日：2021-09-14

申请号：US16857937

申请日：2020-04-24

Applicant: STMicroelectronics (Rousset) SAS

Inventor： François Tailliet ,  Marc Battista

IPC: G11C16/12 ,  G11C16/04 ,  G11C16/08 ,  G11C16/24 ,  G11C16/30

Abstract: A method for programming a non-volatile memory (NVM) and an integrated circuit is disclosed. In an embodiment an integrated circuit includes a memory plane organized into rows and columns of memory words, each memory word comprising memory cells and each memory cell including a state transistor having a control gate and a floating gate and write circuitry configured to program a selected memory word during a programming phase by applying a first nonzero positive voltage to control gates of the state transistors of the memory cells that do not belong to the selected memory word.

公开(公告)号：US20190341114A1

公开(公告)日：2019-11-07

申请号：US16511703

申请日：2019-07-15

Applicant: STMicroelectronics (Rousset) SAS

Inventor： François Tailliet ,  Marc Battista

IPC: G11C16/14 ,  G11C16/04 ,  G11C8/14 ,  G11C8/12 ,  G11C16/08 ,  G11C8/08 ,  G11C5/02 ,  G11C8/10

Abstract: A non-volatile memory device includes a substrate, a plurality of memory words, a control block, a first electrically-conducting link, and a plurality of second electrically-conducting links. The substrate includes a substantially planar surface. The memory words include B memory words disposed at the substantially planar surface. The control block includes B control elements disposed at the substantially planar surface. The first electrically-conducting link is disposed in a first plane parallel to the substantially planar surface. The first electrically-conducting link connects one of the B control elements to a memory word of the memory words. The plurality of second electrically-conducting links includes B-1 second electrically-conducting links respectively connecting B-1 remaining control elements to B-1 corresponding memory words of the plurality of memory words. The B-1 second electrically-conducting links are disposed above the first plane and physically extend at least partially over at least two memory words of the memory words.

公开(公告)号：US10304524B2

公开(公告)日：2019-05-28

申请号：US15630614

申请日：2017-06-22

Applicant: STMicroelectronics (Rousset) SAS

Inventor： François Tailliet ,  Marc Battista

IPC: H01L29/788 ,  G11C11/41 ,  G11C11/412 ,  G11C14/00 ,  G11C16/04 ,  H01L27/11 ,  H01L23/522 ,  H01L29/08 ,  H01L29/423 ,  H01L29/51

Abstract: A semiconductor structure includes first and second source/drain region disposed in a semiconductor body and spaced from each other by a channel region. A gate electrode overlies the channel region and a capacitor electrode is disposed between the gate electrode and the channel region. A first gate dielectric is disposed between the gate electrode and the capacitor electrode and a second gate dielectric disposed between the capacitor electrode and the channel region. A first electrically conductive contact region is in electrical contact with the gate electrode and a second electrically conductive contact region in electrical contact with the capacitor electrode. The first and second contact regions are electrically isolated from one another.

公开(公告)号：US10186320B2

公开(公告)日：2019-01-22

申请号：US15659891

申请日：2017-07-26

Applicant: STMicroelectronics (Rousset) SAS

Inventor： François Tailliet ,  Marc Battista ,  Victorien Brecte

IPC: G11C7/00 ,  G11C16/26 ,  G11C7/06 ,  G11C16/04 ,  G11C16/24

Abstract: A read amplifier of a memory device has two current generators, an inverter, and five transistors. The inverter is connected to the second current generator. The first transistor has a gate connected to the read amplifier, a drain connected to the first current generator, and a source connected to a reference ground. The second transistor has a gate connected to the first current generator, a drain connected to a reference voltage, and a source connected to the gate of the first transistor. The third transistor has a drain connected to the first current generator and a source connected to the reference ground. The fourth transistor has a gate connected to the first current generator, a drain connected to the second current generator, and a source connected to the reference ground. The fifth transistor has a drain connected to the second current generator and a source connected to the reference voltage.

公开(公告)号：US20180300085A1

公开(公告)日：2018-10-18

申请号：US15900481

申请日：2018-02-20

Applicant: STMicroelectronics (Rousset) SAS

Inventor： François Tailliet ,  Marc Battista

IPC: G06F3/06 ,  G06F11/10 ,  G11C29/52

Abstract: A method of writing in a memory of the EEPROM type includes, in the presence of a string of new bytes to be written in the memory plane in at least one destination memory word already containing old bytes, a verification for each destination memory word whether or not the old bytes of this destination memory word must all be replaced with new bytes. The method also includes a reading of the old bytes of this destination memory word only if the old bytes must not all be replaced with new bytes.