公开(公告)号：US11818901B2

公开(公告)日：2023-11-14

申请号：US17489425

申请日：2021-09-29

Applicant: STMicroelectronics (Rousset) SAS ,  STMicroelectronics (Crolles 2) SAS

Inventor： Philippe Boivin ,  Jean Jacques Fagot ,  Emmanuel Petitprez ,  Emeline Souchier ,  Olivier Weber

IPC: H01L21/8222 ,  H10B63/00 ,  H10N70/20 ,  H10N70/00

CPC classification number: H10B63/32 ,  H10N70/231 ,  H10N70/826

Abstract: The disclosure relates to integrated circuits and methods including one or more rows of transistors. In an embodiment, an integrated circuit includes a row of bipolar transistors including a plurality of first conduction regions, a second conduction region, and a common base between the first conduction regions and the second conduction region. An insulating trench is in contact with each bipolar transistor of the row of bipolar transistors. A conductive layer is on the insulating trench and the common base between the first conduction regions. A spacer layer is between the conductive layer and the first conduction regions.

公开(公告)号：US11653582B2

公开(公告)日：2023-05-16

申请号：US16184246

申请日：2018-11-08

Applicant: STMicroelectronics (Crolles 2) SAS ,  STMicroelectronics (Grenoble 2) SAS ,  STMicroelectronics (Rousset) SAS

Inventor： Franck Arnaud ,  David Galpin ,  Stephane Zoll ,  Olivier Hinsinger ,  Laurent Favennec ,  Jean-Pierre Oddou ,  Lucile Broussous ,  Philippe Boivin ,  Olivier Weber ,  Philippe Brun ,  Pierre Morin

IPC: H01L45/00 ,  H01L27/24 ,  G11C13/00

CPC classification number: H10N70/8616 ,  G11C13/0004 ,  G11C13/0069 ,  H10B63/30 ,  H10B63/80 ,  H10N70/011 ,  H10N70/021 ,  H10N70/231 ,  H10N70/826 ,  H10N70/8265 ,  H10N70/8413 ,  H10N70/882 ,  G11C2013/008

Abstract: An electronic chip includes memory cells made of a phase-change material and a transistor. First and second vias extend from the transistor through an intermediate insulating layer to a same height. A first metal level including a first interconnection track in contact with the first via is located over the intermediate insulating layer. A heating element for heating the phase-change material is located on the second via, and the phase-change material is located on the heating element. A second metal level including a second interconnection track is located above the phase-change material. A third via extends from the phase-change material to the second interconnection track.

公开(公告)号：US20170213910A1

公开(公告)日：2017-07-27

申请号：US15483299

申请日：2017-04-10

Applicant: STMicroelectronics (Crolles 2) SAS ,  Commissariat A L'Energie Atomique et aux Energies Alternatives

Inventor： Frederic Boeuf ,  Olivier Weber

IPC: H01L29/78 ,  H01L29/16 ,  H01L21/8238 ,  H01L27/092 ,  H01L21/02 ,  H01L21/762 ,  H01L29/06 ,  H01L29/161

CPC classification number: H01L29/7847 ,  H01L21/02381 ,  H01L21/02422 ,  H01L21/02532 ,  H01L21/02639 ,  H01L21/02667 ,  H01L21/76264 ,  H01L21/76283 ,  H01L21/823807 ,  H01L21/84 ,  H01L27/092 ,  H01L27/12 ,  H01L27/1203 ,  H01L29/0611 ,  H01L29/0642 ,  H01L29/16 ,  H01L29/161 ,  H01L29/7838

Abstract: A substrate of the silicon on insulator type includes a semi-conducting film disposed on a buried insulating layer which is disposed on an unstressed silicon support substrate. The semi-conducting film includes a first film zone of tensile-stressed silicon and a second film zone of tensile-relaxed silicon. Openings through the buried insulating layer permit access to the unstressed silicon support substrate under the first and second film zones. An N channel transistor is formed from the first film zone and a P channel transistor is formed from the second film zone. The second film zone may comprise germanium enriched silicon forming a compressive-stressed region.

公开(公告)号：US20170117296A1

公开(公告)日：2017-04-27

申请号：US15296205

申请日：2016-10-18

Applicant: STMicroelectronics (Crolles 2) SAS ,  Commissariat A L'Energie Atomique et aux Energies Alternatives

Inventor： Sonarith Chhun ,  Emmanuel Josse ,  Gregory Bidal ,  Dominique Golanski ,  Francois Andrieu ,  Jerome Mazurier ,  Olivier Weber

IPC: H01L27/12 ,  H01L29/66 ,  H01L21/306 ,  H01L21/8234 ,  H01L21/02 ,  H01L27/092 ,  H01L29/08 ,  H01L29/417 ,  H01L21/8238 ,  H01L21/84

CPC classification number: H01L27/1203 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/02529 ,  H01L21/02532 ,  H01L21/30608 ,  H01L21/823418 ,  H01L21/823437 ,  H01L21/823468 ,  H01L21/823814 ,  H01L21/823828 ,  H01L21/823864 ,  H01L21/84 ,  H01L27/0922 ,  H01L29/0847 ,  H01L29/16 ,  H01L29/1608 ,  H01L29/161 ,  H01L29/41783 ,  H01L29/6653

Abstract: A device includes both low-voltage (LV) and high-voltage (HV) metal oxide semiconductor (MOS) transistors of opposite types. Gate stacks for the transistors are formed over a semiconductor layer. First spacers made of a first insulator are provided on the gate stacks of the LV and HV MOS transistors. Second spacers made of a second insulator are provided on the gate stacks of the HV MOS transistors only. The insulators are selectively removed to expose the semiconductor layer. Epitaxial growth of semiconductor material is made from the exposed semiconductor layer to form raised source-drain structures that are separated from the gate stacks by the first spacers for the LV MOS transistors and the second spacers for the HV MOS transistors.

公开(公告)号：US11723220B2

公开(公告)日：2023-08-08

申请号：US17244514

申请日：2021-04-29

Applicant: STMicroelectronics (Crolles 2) SAS

Inventor： Remy Berthelon ,  Olivier Weber

IPC: H10B63/00

CPC classification number: H10B63/32 ,  H10B63/80

Abstract: A method for manufacturing an electronic chip includes providing a semiconductor layer located on an insulator covering a semiconductor substrate. First and second portions of the semiconductor layer are oxidized up to the insulator. Stresses are generated in third portions of the semiconductor layer, and each of the third portions extend between two portions of the semiconductor layer that are oxidized. Cavities are formed which extend at least to the substrate through the second portions and the insulator. Bipolar transistors are formed in at least part of the cavities and first field effect transistors are formed in and on the third portions. Phase change memory points are coupled to the bipolar transistors.

公开(公告)号：US10381478B2

公开(公告)日：2019-08-13

申请号：US15483299

申请日：2017-04-10

Applicant: STMicroelectronics (Crolles 2) SAS ,  Commissariat A L'Energie Atomique et aux Energies Alternatives

Inventor： Frederic Boeuf ,  Olivier Weber

IPC: H01L23/48 ,  H01L29/04 ,  H01L29/78 ,  H01L21/02 ,  H01L21/84 ,  H01L27/12 ,  H01L29/06 ,  H01L21/762 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/16 ,  H01L29/161

Abstract: A substrate of the silicon on insulator type includes a semi-conducting film disposed on a buried insulating layer which is disposed on an unstressed silicon support substrate. The semi-conducting film includes a first film zone of tensile-stressed silicon and a second film zone of tensile-relaxed silicon. Openings through the buried insulating layer permit access to the unstressed silicon support substrate under the first and second film zones. An N channel transistor is formed from the first film zone and a P channel transistor is formed from the second film zone. The second film zone may comprise germanium enriched silicon forming a compressive-stressed region.

公开(公告)号：US20180097014A1

公开(公告)日：2018-04-05

申请号：US15722340

申请日：2017-10-02

Applicant: STMicroelectronics (Crolles 2) SAS ,  STMicroelectronics SA ,  Commissariat A L'Energie Atomique et aux Energies Alternatives

Inventor： Vincent Barral ,  Nicolas Planes ,  Antoine Cros ,  Sebastien Haendler ,  Thierry Poiroux ,  Olivier Weber ,  Patrick Scheer

IPC: H01L27/12

CPC classification number: H01L27/1203 ,  B82Y99/00

Abstract: An electronic chip includes FDSOI-type field-effect transistors. The transistor each have a channel region that is doped at an average level in a range from 1016 to 5*1017 atoms/cm3 with a conductivity type opposite to that of a conductivity type for the dopant in the drain and source regions.

公开(公告)号：US20170271325A1

公开(公告)日：2017-09-21

申请号：US15454788

申请日：2017-03-09

Applicant: STMicroelectronics (Crolles 2) SAS ,  STMicroelectronics (Rousset) SAS ,  Commissariat A L'Energie Atomique et aux Energies Alternatives

Inventor： Olivier Weber ,  Emmanuel Richard ,  Philippe Boivin

IPC: H01L27/06 ,  H01L27/24 ,  H01L29/732 ,  H01L21/84 ,  H01L21/8249 ,  H01L45/00

CPC classification number: H01L27/0623 ,  H01L21/8249 ,  H01L21/84 ,  H01L27/1207 ,  H01L27/2445 ,  H01L29/0813 ,  H01L29/41708 ,  H01L29/66303 ,  H01L29/732 ,  H01L45/06 ,  H01L45/1206 ,  H01L45/1233 ,  H01L45/126 ,  H01L45/16

Abstract: Bipolar transistors and MOS transistors are formed in a common process. A semiconductor layer is arranged on an insulating layer. On a side of the bipolar transistors: an insulating region including the insulating layer is formed; openings are etched through the insulating region to delimit insulating walls; the openings are filled with first epitaxial portions; and the first epitaxial portions and a first region extending under the first epitaxial portions and under the insulating walls are doped. On the side of the bipolar transistors and on a side of the MOS transistors: gate structures are formed; second epitaxial portions are made; and the second epitaxial portions covering the first epitaxial portions are doped.

公开(公告)号：US09099354B2

公开(公告)日：2015-08-04

申请号：US14309385

申请日：2014-06-19

Applicant: Commissariat a l'energie atomique et aux energies alternatives ,  STMicroelectronics (Crolles 2) SAS

Inventor： Olivier Weber ,  Nicolas Planes ,  Rossella Ranica

IPC: H01L27/12 ,  H01L27/092

CPC classification number: H01L27/1203 ,  H01L21/7624 ,  H01L21/76264 ,  H01L21/84 ,  H01L27/092 ,  H01L27/0922 ,  H01L27/0928 ,  H01L29/78648

Abstract: The invention relates to an integrated circuit comprising a semi-conducting substrate and first and second cells. Each cell comprises first and second transistors of nMOS and pMOS type including first and second gate stacks including a gate metal. There are first and second ground planes under the first and second transistors and an oxide layer extending between the transistors and the ground planes. The gate metals of the nMOS and of a pMOS exhibit a first work function and the gate metal of the other pMOS exhibiting a second work function greater than the first work function. The difference between the work functions is between 55 and 85 meV and the first work function Wf1 satisfies the relation Wfmg−0.04−0.005*Xge

Abstract translation: 本发明涉及包括半导体衬底和第一和第二单元的集成电路。 每个单元包括nMOS和pMOS型的第一和第二晶体管，包括包括栅极金属的第一和第二栅极堆叠。 在第一和第二晶体管之下有第一和第二接地层，以及在晶体管和接地层之间延伸的氧化物层。 nMOS和pMOS的栅极金属表现出第一功函数，另一个pMOS的栅极金属表现出大于第一功函数的第二功函数。 工作函数之间的差异在55和85meV之间，第一功函数Wf1满足关系Wfmg-0.04-0.005 * Xge

公开(公告)号：US20150021692A1

公开(公告)日：2015-01-22

申请号：US14220542

申请日：2014-03-20

Applicant: Commissariat A L'Energie Atomique et aux Energies Alternatives ,  STMicroelectronics (Crolles 2) SAS

Inventor： Frederic Boeuf ,  Olivier Weber

IPC: H01L29/06 ,  H01L21/02 ,  H01L27/12 ,  H01L21/84

CPC classification number: H01L29/7847 ,  H01L21/02381 ,  H01L21/02422 ,  H01L21/02532 ,  H01L21/02639 ,  H01L21/02667 ,  H01L21/76264 ,  H01L21/76283 ,  H01L21/823807 ,  H01L21/84 ,  H01L27/092 ,  H01L27/12 ,  H01L27/1203 ,  H01L29/0611 ,  H01L29/0642 ,  H01L29/16 ,  H01L29/161 ,  H01L29/7838

Abstract: A substrate of the silicon on insulator type includes a semi-conducting film disposed on a buried insulating layer which is disposed on an unstressed silicon support substrate. The semi-conducting film includes a first film zone of tensile-stressed silicon and a second film zone of tensile-relaxed silicon. Openings through the buried insulating layer permit access to the unstressed silicon support substrate under the first and second film zones. An N channel transistor is formed from the first film zone and a P channel transistor is formed from the second film zone. The second film zone may comprise germanium enriched silicon forming a compressive-stressed region.

Abstract translation: 硅绝缘体型的衬底包括设置在埋置绝缘层上的半导电膜，该绝缘层设置在未受压的硅支撑衬底上。 半导电膜包括拉伸应力硅的第一膜区和拉伸松弛硅的第二膜区。 穿过掩埋绝缘层的开口允许在第一和第二膜区下方进入未受压的硅支撑基板。 由第一膜区形成N沟道晶体管，并且由第二膜区形成P沟道晶体管。 第二膜区可以包括形成压应力区域的富锗的硅。