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公开(公告)号：US20210067148A1
公开(公告)日：2021-03-04
申请号：US16559118
申请日：2019-09-03
Applicant: STMicroelectronics S.r.l.
Inventor： Alessandro BERTOLINI , Alberto CATTANI , Stefano RAMORINI , Alessandro GASPARINI
Abstract: A DC-DC converter includes clock generation circuitry generating first and second clock signals that are out of phase, and a control signal generator generating a switching control signal at an edge of the second clock signal based upon a comparison of an error voltage to a summed voltage. Boost circuitry charges an energy storage component during an on-phase and discharges the energy storage component during an off-phase to thereby generate an output voltage. The on-phase and off-phase are set as a function of the switching control signal. Sum voltage generation circuitry generates a ramp voltage in response to an edge of the first clock signal and generates the summed voltage at an edge of the second clock signal. The sum voltage represents a sum of the ramp voltage and a voltage representative of the current flowing in the energy storage component during the on-phase.
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公开(公告)号：US20220166315A1
公开(公告)日：2022-05-26
申请号：US17533338
申请日：2021-11-23
Applicant: STMicroelectronics S.r.l.
Inventor： Stefano RAMORINI , Alessandro GASPARINI , Alberto CATTANI
IPC: H02M3/07
Abstract: Charge pump stages are coupled between flying capacitor pairs and arranged in a cascaded between a bottom voltage line and an output voltage line. Gain stages apply pump phase signals having a certain amplitude to the charge pump stages via the flying capacitors. A feedback signal path from the output voltage line to the bottom voltage line applies a feedback control signal to the bottom voltage line. Power supply for the gain stages is provided by a voltage of the feedback control signal in order to control the amplitude of the pump phase signals. An asynchronous logic circuit generates the switching drive signals for the gain stages with a certain switching frequency which is a function of a logic supply voltage derived from the voltage of the feedback control signal.
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公开(公告)号：US20210074835A1
公开(公告)日：2021-03-11
申请号：US16561670
申请日：2019-09-05
Applicant: STMicroelectronics S.r.l.
Inventor： Alberto CATTANI , Alessandro GASPARINI
IPC: H01L29/739 , H02M1/32 , H02M3/158
Abstract: A power MOS stage includes a first power MOS device and a second power MOS devices connected in parallel between a first node and a second node, the first power MOS device having a first voltage rating and the second power MOS device having a second voltage rating that is lower than the first voltage rating. A driver circuit is configured to drive control nodes of the first and second power MOS devices in a sequential manner when actuating the power MOS stage by actuating the first power MOS device before actuating the second power MOS device. The control nodes of the first and second power MOS devices are further driven in a sequential manner when deactuating the power MOS stage by deactuating the second power MOS device before deactuating the first power MOS device.
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公开(公告)号：US20190372535A1
公开(公告)日：2019-12-05
申请号：US16539478
申请日：2019-08-13
Applicant: STMicroelectronics S.r.l.
Inventor： Stefano RAMORINI , Alberto CATTANI , Germano NICOLLINI , Alessandro GASPARINI
Abstract: A switching amplifier, such as a Class D amplifier, includes a current sensing circuit. The current sensing circuit is formed by replica loop circuits that are selectively coupled to corresponding output inverter stages of the switching amplifier. The replica loop circuits operated to produce respective replica currents of the output currents generated by the output inverter stages. A sensing circuitry is coupled to receive the replica currents from the replica loop circuits and operates to produce an output sensing signal as a function of the respective replica currents.
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公开(公告)号：US20180337647A1
公开(公告)日：2018-11-22
申请号：US15982548
申请日：2018-05-17
Applicant: STMicroelectronics S.r.l.
Inventor： Stefano RAMORINI , Alberto CATTANI , Alessandro GASPARINI , Germano NICOLLINI
CPC classification number: H03F3/45192 , H03F2200/18 , H03M1/124 , H03M1/66 , H03M1/68 , H03M1/742 , H03M1/765
Abstract: A circuit includes an input transistor pair with first and second input transistors, the first input transistor having a control terminal configured to receive an input signal and a cascode transistor pair including a first and second cascode transistors having a common control node. A bias circuit has a bias input configured to receive the input signal and a first bias output coupled to the common node of the first and second cascode transistors. The bias circuit includes a signal tracking circuit operating to generate the first bias output to track the input signal. A pair of load transistors are coupled to the input transistor pair and biased by a second bias output of the bias circuit.
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Patent Agency Ranking
公开(公告)号：US20170129773A1
公开(公告)日：2017-05-11
申请号：US15410394
申请日：2017-01-19
Applicant: STMICROELECTRONICS S.R.L.
CPC classification number: B81B7/008 , B81B3/00 , B81B7/04 , B81B2201/0257 , B81B2207/03 , B81B2207/053 , H04R3/007 , H04R3/12 , H04R19/005 , H04R2201/003
Abstract: A system for driving a MEMS array having a number of MEMS structures, each defining at least one row terminal and one column terminal, envisages: a number of row driving stages, each for supplying row-biasing signals to the row terminal of each MEMS structure associated to a respective row; a number of column driving stages, each for supplying column-biasing signals to the column terminal of each MEMS structure associated to a respective column; and a control unit, for supplying row-address signals to the row driving stages for generation of the row-biasing signals and for supplying column-address signals to the column driving stages for generation of the column-biasing signals. The control unit further supplies row-deactivation and/or column-deactivation signals to one or more of the row and column driving stages, for causing deactivation of one or more rows and/or columns of the MEMS array.
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公开(公告)号：US20240348249A1
公开(公告)日：2024-10-17
申请号：US18630493
申请日：2024-04-09
Applicant: STMicroelectronics S.r.l.
Inventor： Francesco PINZIN , Alessandro BERTOLINI , Alberto CATTANI
IPC: H03K17/687 , H02M1/088 , H02M3/157 , H02M3/158
CPC classification number: H03K17/6871 , H02M1/088 , H02M3/157 , H02M3/158
Abstract: A power MOSFET driver circuit includes a feedback circuit configured to supply a feedback signal that signals when a gate voltage of the power MOSFET crosses a plateau value and the power MOSFET switches conduction state. The feedback circuit includes a comparator with a replica MOSFET of the power MOSFET, with scaled down dimensions, whose gate is coupled to the gate electrode of the power MOSFET. A bistable circuit has an input coupled to an output of the replica MOSFET and is configured to change a logic state of the feedback signal following the transition of the switching signal when the gate voltage of the power MOSFET crosses the plateau value and the power MOSFET switches conduction state.
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公开(公告)号：US20240120838A1
公开(公告)日：2024-04-11
申请号：US18376328
申请日：2023-10-03
Applicant: STMicroelectronics S.r.l.
Inventor： Alessandro BERTOLINI , Alberto CATTANI , Alessandro GASPARINI
CPC classification number: H02M3/158 , H02M1/0035
Abstract: In a DC-DC converter, a duty-cycle control signal is generated in response to comparing the switching stage output voltage and a reference voltage signal. A first circuit compares the duty-cycle control signal and a ramp to produce a PWM signal. A second circuit compares the duty-cycle control signal and a skip threshold to produce a skip control signal which halts switching operation of the switching stage. A count is made of number of periods of the skip control signal during a monitoring time window and the number of periods of a clock signal during a period of the skip control signal is counted. When the counted number of skip control signal periods is within a first range and the counted number of clock signal periods is within a second range, a common detection signal is asserted to trigger varying a value of the skip threshold signal.
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19.发明公开公开(公告)号：US20240006994A1
公开(公告)日：2024-01-04
申请号：US18214646
申请日：2023-06-27
Applicant: STMicroelectronics S.r.l.
Inventor： Tommaso ROSA , Alessandro BERTOLINI , Stefano RAMORINI , Alberto CATTANI
IPC: H02M3/158
CPC classification number: H02M3/158
Abstract: A DC-DC boost converter includes an input receiving an input voltage and an output producing an output voltage. A switching stage is formed by a low-side transistor arranged between a switching node and a ground node, and a high-side transistor arranged between the switching node and the output. The high-side transistor includes a body diode having an anode coupled to the switching node and a cathode coupled to the output. The converter is controlled in an asynchronous operation mode where the low-side transistor is driven alternately to a conductive state and a non-conductive state, and the high-side transistor is driven steadily to a non-conductive state. A variable load circuit is selectively coupled between the two output terminals when the converter is in the asynchronous operation mode in order to sink a load current having a value that is a function of a value of the input voltage.
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公开(公告)号：US20230216404A1
公开(公告)日：2023-07-06
申请号：US18089736
申请日：2022-12-28
Applicant: STMicroelectronics S.r.l.
Inventor： Alessandro BERTOLINI , Alberto CATTANI , Alessandro GASPARINI
Abstract: A supply node receives supply voltage and an output node provides a regulated output voltage to a load. A switching transistor is coupled between the supply and output nodes. The switching transistor is controlled by a drive signal generated by a control circuit to control switching activity. The control circuit includes circuitry to sense a feedback voltage indicative of the regulated output voltage and a comparator generating a comparison logic signal dependent on a comparison of the feedback voltage to a reference. A logic circuit generates a skip signal in response to the comparison logic signal. A counter generates a termination signal. Signal processing circuitry controls the switching activity by asserting the drive signal as a function of the skip signal and the termination signal.
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