公开(公告)号：US20060043599A1

公开(公告)日：2006-03-02

申请号：US10932296

申请日：2004-09-02

申请人： Salman Akram ,  Charles Watkins ,  Mark Hiatt ,  David Hembree ,  James Wark ,  Warren Farnworth ,  Mark Tuttle ,  Sidney Rigg ,  Steven Oliver ,  Kyle Kirby ,  Alan Wood ,  Lu Velicky

发明人： Salman Akram ,  Charles Watkins ,  Mark Hiatt ,  David Hembree ,  James Wark ,  Warren Farnworth ,  Mark Tuttle ,  Sidney Rigg ,  Steven Oliver ,  Kyle Kirby ,  Alan Wood ,  Lu Velicky

IPC分类号： H01L21/44 ,  H01L23/48

CPC分类号： H01L21/76877 ,  H01L21/6835 ,  H01L21/76898 ,  H01L23/481 ,  H01L24/45 ,  H01L27/14634 ,  H01L27/14636 ,  H01L2221/6834 ,  H01L2224/02166 ,  H01L2224/0554 ,  H01L2224/05567 ,  H01L2224/05573 ,  H01L2224/16 ,  H01L2224/45144 ,  H01L2224/48463 ,  H01L2924/00014 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/0105 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/04941 ,  H01L2924/10253 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/00 ,  H01L2224/05599 ,  H01L2224/0555 ,  H01L2224/0556

摘要： A through-wafer interconnect for imager, memory and other integrated circuit applications is disclosed, thereby eliminating the need for wire bonding, making devices incorporating such interconnects stackable and enabling wafer level packaging for imager devices. Further, a smaller and more reliable die package is achieved and circuit parasitics (e.g., L and R) are reduced due to the reduced signal path lengths.

公开(公告)号：US20060008739A1

公开(公告)日：2006-01-12

申请号：US11216938

申请日：2005-08-31

申请人： Alan Wood ,  Warren Farnworth ,  David Hembree ,  Sidney Rigg ,  William Hiatt ,  Peter Benson ,  Kyle Kirby ,  Salman Akram

发明人： Alan Wood ,  Warren Farnworth ,  David Hembree ,  Sidney Rigg ,  William Hiatt ,  Peter Benson ,  Kyle Kirby ,  Salman Akram

IPC分类号： G03C1/00

CPC分类号： G03F7/0037 ,  B33Y30/00 ,  B33Y70/00 ,  B33Y80/00 ,  G03F7/0047

摘要： Materials for use in programmed material consolidation processes, such as stereolithography, include a selectively consolidatable material and a filler. The filler may be included to optimize one or more physical properties of the material. The material is both selectively consolidatable and includes the desired physical property. Examples of physical properties that may optimized in a selectively consolidatable compound by mixing a filler material with a selectively consolidatable material include, without limitation, coefficient of thermal expansion, rigidity, fracture toughness, thermal stability, and strength.

摘要翻译： 用于程序化材料固结方法（例如立体光刻）的材料包括可选择的可固结材料和填料。 可以包括填料以优化材料的一种或多种物理性质。 该材料既可选择性地整合，并且包括所需的物理性质。 通过将填充材料与可选择性地可固结的材料混合可以在可选择地可固化的化合物中优化的物理性质的实例包括但不限于热膨胀系数，刚性，断裂韧性，热稳定性和强度。

公开(公告)号：US20060003255A1

公开(公告)日：2006-01-05

申请号：US11216599

申请日：2005-08-31

申请人： Alan Wood ,  Warren Farnworth ,  David Hembree ,  Sidney Rigg ,  William Hiatt ,  Peter Benson ,  Kyle Kirby ,  Salman Akram

发明人： Alan Wood ,  Warren Farnworth ,  David Hembree ,  Sidney Rigg ,  William Hiatt ,  Peter Benson ,  Kyle Kirby ,  Salman Akram

IPC分类号： G03C1/492

CPC分类号： G03F7/0037 ,  B33Y30/00 ,  B33Y70/00 ,  B33Y80/00 ,  G03F7/0047

摘要： Methods for optimizing physical properties of selectively consolidatable materials, such as photoimageable materials, include mixing filler materials with the selectively consolidatable materials. The resulting compound has the desired physical property, as well as selective consolidatability. Examples of physical properties that may optimized in a selectively consolidatable compound by mixing a filler material with a selectively consolidatable material include, without limitation, coefficient of thermal expansion, rigidity, fracture toughness, thermal stability, and strength.

摘要翻译： 用于优化选择性可固结材料（例如可光成像材料）的物理性质的方法包括将填料与可选择的可固结材料混合。 所得化合物具有所需的物理性质以及选择性的可固化性。 通过将填充材料与可选择性地可固结的材料混合可以在可选择地可固化的化合物中优化的物理性质的实例包括但不限于热膨胀系数，刚性，断裂韧性，热稳定性和强度。

公开(公告)号：US20060001139A1

公开(公告)日：2006-01-05

申请号：US11216617

申请日：2005-08-31

申请人： Alan Wood ,  Warren Farnworth ,  David Hembree ,  Sidney Rigg ,  William Hiatt ,  Peter Benson ,  Kyle Kirby ,  Salman Akram

发明人： Alan Wood ,  Warren Farnworth ,  David Hembree ,  Sidney Rigg ,  William Hiatt ,  Peter Benson ,  Kyle Kirby ,  Salman Akram

IPC分类号： H01L23/02

CPC分类号： G03F7/0037 ,  B33Y30/00 ,  B33Y70/00 ,  B33Y80/00 ,  G03F7/0047

摘要： A support structure for use with a semiconductor substrate in thinning, or backgrinding, thereof, as well as during post-thinning processing of the semiconductor substrate includes a portion which extends substantially along and around an outer periphery of the semiconductor substrate to impart the thinned semiconductor substrate with rigidity. The support structure may be configured as a ring or as a member which substantially covers an active surface of the semiconductor substrate and forms a protective structure over each semiconductor device carried by the active surface.

摘要翻译： 在半导体衬底的薄化或后研磨以及后稀化处理期间与半导体衬底一起使用的支撑结构包括基本上沿半导体衬底的外周延伸并且围绕半导体衬底的外周延伸的部分，以使薄化半导体 基板具有刚性。 支撑结构可以被配置为环或作为基本上覆盖半导体衬底的有源表面并且在由有源表面承载的每个半导体器件上形成保护结构的构件。

公开(公告)号：US20050064681A1

公开(公告)日：2005-03-24

申请号：US10666742

申请日：2003-09-19

申请人： Alan Wood ,  Warren Farnworth ,  David Hembree ,  Sidney Rigg ,  William Hiatt ,  Peter Benson ,  Kyle Kirby ,  Salman Akram

发明人： Alan Wood ,  Warren Farnworth ,  David Hembree ,  Sidney Rigg ,  William Hiatt ,  Peter Benson ,  Kyle Kirby ,  Salman Akram

IPC分类号： E21B43/02 ,  G03F7/00 ,  G03F7/004 ,  H01L21/30 ,  H01L21/46

CPC分类号： G03F7/0037 ,  B33Y30/00 ,  B33Y70/00 ,  B33Y80/00 ,  G03F7/0047

摘要： A support structure for use with a semiconductor substrate in thinning, or backgrinding, thereof, as well as during post-thinning processing of the semiconductor substrate includes a portion which extends substantially along and around an outer periphery of the semiconductor substrate to impart the thinned semiconductor substrate with rigidity. The support structure may be configured as a ring or as a member which substantially covers an active surface of the semiconductor substrate and forms a protective structure over each semiconductor device carried by the active surface. Assemblies that include the support structure and a semiconductor substrate are also within the scope of the present invention, as are methods for forming the support structures and thinning and post-thinning processes that include use of the support structures.

摘要翻译： 在半导体衬底的薄化或后研磨以及后稀化处理期间与半导体衬底一起使用的支撑结构包括基本上沿半导体衬底的外周延伸并且围绕半导体衬底的外周延伸的部分，以使薄化半导体 基板具有刚性。 支撑结构可以被配置为环或作为基本上覆盖半导体衬底的有源表面并且在由有源表面承载的每个半导体器件上形成保护结构的构件。 包括支撑结构和半导体衬底的组件也在本发明的范围内，形成支撑结构的方法和包括使用支撑结构的减薄和后变薄工艺也是如此。

公开(公告)号：US20060003549A1

公开(公告)日：2006-01-05

申请号：US11216866

申请日：2005-08-31

申请人： Alan Wood ,  Warren Farnworth ,  David Hembree ,  Sidney Rigg ,  William Hiatt ,  Peter Benson ,  Kyle Kirby ,  Salman Akram

发明人： Alan Wood ,  Warren Farnworth ,  David Hembree ,  Sidney Rigg ,  William Hiatt ,  Peter Benson ,  Kyle Kirby ,  Salman Akram

IPC分类号： H01L21/30

CPC分类号： G03F7/0037 ,  B33Y30/00 ,  B33Y70/00 ,  B33Y80/00 ,  G03F7/0047

摘要： A fabrication substrate for use in fabricating integrated circuits and other electronic devices includes a substrate that comprises semiconductor material, as well as a support structure on an active surface of the substrate. The support structure is located at or adjacent to an entire outer peripheral edge of the substrate. The support structure may be configured as a ring-like element or as a member which substantially covers an active surface of the semiconductor substrate and forms a protective structure over each semiconductor device carried by the active surface.

摘要翻译： 用于制造集成电路和其它电子器件的制造衬底包括：衬底，其包含半导体材料，以及在衬底的有源表面上的支撑结构。 支撑结构位于或邻近基板的整个外周边缘。 支撑结构可以被构造为环状元件或者作为基本上覆盖半导体衬底的有源表面并且在由有源表面承载的每个半导体器件上形成保护结构的构件。

公开(公告)号：US20050287783A1

公开(公告)日：2005-12-29

申请号：US10879838

申请日：2004-06-29

申请人： Kyle Kirby ,  Salman Akram ,  David Hembree ,  Sidney Rigg ,  Warren Farnworth ,  William Hiatt

发明人： Kyle Kirby ,  Salman Akram ,  David Hembree ,  Sidney Rigg ,  Warren Farnworth ,  William Hiatt

IPC分类号： H01L21/44 ,  H01L21/4763 ,  H01L21/768 ,  H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H05K1/03 ,  H05K3/40 ,  H05K3/42

CPC分类号： H01L21/76898 ,  H01L23/481 ,  H01L24/48 ,  H01L2224/48091 ,  H01L2224/48465 ,  H01L2924/00014 ,  H01L2924/01046 ,  H01L2924/01077 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/12042 ,  H01L2924/14 ,  H05K1/0306 ,  H05K3/4038 ,  H05K3/422 ,  H05K3/423 ,  H05K2201/0305 ,  H05K2201/09827 ,  H05K2203/072 ,  H05K2203/1147 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： Microelectronic devices, methods for packaging microelectronic devices, and methods for forming interconnects in microelectronic devices are disclosed herein. In one embodiment, a method comprises providing a microelectronic substrate having a front side and a backside. The substrate has a microelectronic die including an integrated circuit and a terminal operatively coupled to the integrated circuit. The method also includes forming a passage at least partially through the substrate and having an opening at the front side and/or backside of the substrate. The method further includes sealing the opening with a conductive cap that closes one end of the passage while another end of the passage remains open. The method then includes filling the passage with a conductive material.

摘要翻译： 本文公开了微电子器件，用于封装微电子器件的方法，以及用于在微电子器件中形成互连的方法。 在一个实施例中，一种方法包括提供具有正面和背面的微电子衬底。 衬底具有包括集成电路的微电子管芯和可操作地耦合到集成电路的端子。 该方法还包括至少部分地形成通过基底并且在基底的前侧和/或后侧具有开口的通道。 该方法还包括用封闭通道一端的导电盖密封开口，同时通道的另一端保持打开。 该方法然后包括用导电材料填充通道。

公开(公告)号：US20060199363A1

公开(公告)日：2006-09-07

申请号：US11416824

申请日：2006-05-03

申请人： Kyle Kirby ,  Salman Akram ,  David Hembree ,  Sidney Rigg ,  Warren Farnworth ,  William Hiatt

发明人： Kyle Kirby ,  Salman Akram ,  David Hembree ,  Sidney Rigg ,  Warren Farnworth ,  William Hiatt

IPC分类号： H01L21/44

CPC分类号： H01L21/76898 ,  H01L23/481 ,  H01L24/48 ,  H01L2224/48091 ,  H01L2224/48465 ,  H01L2924/00014 ,  H01L2924/01046 ,  H01L2924/01077 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/12042 ,  H01L2924/14 ,  H05K1/0306 ,  H05K3/4038 ,  H05K3/422 ,  H05K3/423 ,  H05K2201/0305 ,  H05K2201/09827 ,  H05K2203/072 ,  H05K2203/1147 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： Microelectronic devices, methods for packaging microelectronic devices, and methods for forming interconnects in microelectronic devices are disclosed herein. In one embodiment, a method comprises providing a microelectronic substrate having a front side and a backside. The substrate has a microelectronic die including an integrated circuit and a terminal operatively coupled to the integrated circuit. The method also includes forming a passage at least partially through the substrate and having an opening at the front side and/or backside of the substrate. The method further includes sealing the opening with a conductive cap that closes one end of the passage while another end of the passage remains open. The method then includes filling the passage with a conductive material.

公开(公告)号：US20060255826A1

公开(公告)日：2006-11-16

申请号：US11409060

申请日：2006-04-24

申请人： Salman Akram ,  William Hiatt ,  Alan Wood ,  Charles Watkins ,  Kyle Kirby

发明人： Salman Akram ,  William Hiatt ,  Alan Wood ,  Charles Watkins ,  Kyle Kirby

IPC分类号： G01R31/26

CPC分类号： G01R31/2635 ,  G01R31/2831

摘要： Systems and methods for testing microelectronic imagers and microfeature devices are disclosed herein. In one embodiment, a method includes providing a microfeature workpiece including a substrate having a front side, a backside, and a plurality of microelectronic dies. The individual dies include an integrated circuit and a plurality of contact pads at the backside of the substrate operatively coupled to the integrated circuit. The method includes contacting individual contact pads with corresponding pins of a probe card. The method further includes testing the dies. In another embodiment, the individual dies can further comprise an image sensor at the front side of the substrate and operatively coupled to the integrated circuit. The image sensors are illuminated while the dies are tested.

摘要翻译： 本文公开了用于测试微电子成像器和微特征器件的系统和方法。 在一个实施例中，一种方法包括提供微功能工件，其包括具有正面，背面和多个微电子管芯的衬底。 各个管芯包括集成电路和在衬底的背面可操作地耦合到集成电路的多个接触焊盘。 该方法包括使各个接触垫与探针卡的相应引脚接触。 该方法还包括测试模具。 在另一个实施例中，各个管芯还可以包括在衬底的前侧的图像传感器，并可操作地耦合到集成电路。 在测试模具时，图像传感器被照亮。

公开(公告)号：US20050285154A1

公开(公告)日：2005-12-29

申请号：US10879398

申请日：2004-06-29

申请人： Salman Akram ,  Charles Watkins ,  Kyle Kirby ,  Alan Wood ,  William Hiatt

发明人： Salman Akram ,  Charles Watkins ,  Kyle Kirby ,  Alan Wood ,  William Hiatt

IPC分类号： H01L27/146 ,  H01L27/148 ,  H01L31/02 ,  H01L21/00

CPC分类号： H01L27/146 ,  H01L21/76898 ,  H01L27/14618 ,  H01L27/148 ,  H01L31/02016 ,  H01L2224/48227 ,  H01L2924/01046 ,  H01L2924/01066 ,  H01L2924/01077 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/10253 ,  H01L2924/00

摘要： Microelectronic imagers, methods for packaging microelectronic imagers, and methods for forming electrically conductive through-wafer interconnects in microelectronic imagers are disclosed herein. In one embodiment, a microelectronic imaging die can include a microelectronic substrate, an integrated circuit, and an image sensor electrically coupled to the integrated circuit. A bond-pad is carried by the substrate and electrically coupled to the integrated circuit. An electrically conductive through-wafer interconnect extends through the substrate and is in contact with the bond-pad. The interconnect can include a passage extending completely through the substrate and the bond-pad, a dielectric liner deposited into the passage and in contact with the substrate, first and second conductive layers deposited onto at least a portion of the dielectric liner, and a conductive fill material deposited into the passage over at least a portion of the second conductive layer and electrically coupled to the bond-pad.

摘要翻译： 本文公开了微电子成像器，用于封装微电子成像器的方法，以及用于在微电子成像器中形成导电晶片间互连的方法。 在一个实施例中，微电子成像管芯可以包括微电子衬底，集成电路和电耦合到集成电路的图像传感器。 接合焊盘由衬底承载并电耦合到集成电路。 导电晶片互连延伸穿过衬底并与接合焊盘接触。 互连可以包括完全延伸穿过衬底和接合焊盘的通道，沉积到通道中并与衬底接触的电介质衬垫，沉积在电介质衬垫的至少一部分上的第一和第二导电层以及导电 在第二导电层的至少一部分上沉积到通道中并且电耦合到接合焊盘的填充材料。