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    INTEGRATED CIRCUIT DEVICE
    11.
    发明申请
    INTEGRATED CIRCUIT DEVICE 有权

    公开(公告)号：US20210091105A1

    公开(公告)日：2021-03-25

    申请号：US16923636

    申请日：2020-07-08

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Chanho Kim ,  Daeseok Byeon ,  Dongku Kang

    IPC: H01L27/11573 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/11529 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11582 ,  H01L23/535 ,  H01L21/768

    Abstract: An integrated circuit (IC) device includes a peripheral circuit structure, a memory stack including a plurality of gate lines overlapping the peripheral circuit structure in a vertical direction on the peripheral circuit structure, an upper substrate between the peripheral circuit structure and the memory stack, the upper substrate including a through hole positioned below a memory cell region of the memory stack, a word line cut region extending lengthwise in a first lateral direction across the memory stack and the through hole, and a common source line located in the word line cut region, the common source line including a first portion extending lengthwise in the first lateral direction on the upper substrate and a second portion integrally connected to the first portion, the second portion penetrating the upper substrate through the through hole from an upper portion of the upper substrate and extending into the peripheral circuit structure.

    Integrated circuit including power gating circuit
    13.
    发明授权
    Integrated circuit including power gating circuit 有权

    公开(公告)号：US12249984B2

    公开(公告)日：2025-03-11

    申请号：US17886194

    申请日：2022-08-11

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Changyeon Yu ,  Pansuk Kwak ,  Daeseok Byeon

    IPC: H01L27/02 ,  G06F1/26 ,  H03K17/687 ,  H03K19/00 ,  H03K19/003

    Abstract: An integrated circuit includes a logic circuit comprising a plurality of logic transistors, the logic circuit comprising a plurality of logic gate lines extending in a first direction; and a power gating circuit comprising a plurality of power gating transistors, the power gating circuit comprising a first power gate line extending in a second direction that is perpendicular to the first direction, and the power gating circuit being connected to the logic circuit, wherein a plurality of source regions respectively included in the plurality of power gating transistors are connected to each other, or a plurality of drain regions respectively included in the plurality of power gating transistors are connected to each other.

    MEMORY DEVICE INCLUDING PAGE BUFFER CIRCUIT AND SSD INCLUDING THE MEMORY DEVICE, AND METHOD OF USING THE SAME
    15.
    发明公开
    MEMORY DEVICE INCLUDING PAGE BUFFER CIRCUIT AND SSD INCLUDING THE MEMORY DEVICE, AND METHOD OF USING THE SAME 审中-公开

    公开(公告)号：US20240153565A1

    公开(公告)日：2024-05-09

    申请号：US18223278

    申请日：2023-07-18

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Yongsung Cho ,  Daeseok Byeon ,  Minjeong Heo

    IPC: G11C16/24 ,  G11C16/04 ,  G11C16/26

    CPC classification number: G11C16/24 ,  G11C16/0483 ,  G11C16/26

    Abstract: A memory device includes a memory cell array, and a plurality of page buffer units, the page buffer units each including a sensing node, a data transfer node, a first transistor precharging the data transfer node, a second transistor connecting the sensing node to the data transfer node, a sensing latch connected to the data transfer node, a third transistor changing a data value of the sensing latch, and a fourth transistor connecting the third transistor to the data transfer node, wherein, during a sensing operation, in a first time period, the sensing node is precharged based on a first path through the first transistor, the data transfer node, and the fourth transistor, and in a second time period, a voltage of the sensing node is set to a threshold voltage according to a second path through the fourth transistor, the data transfer node, and the third transistor.

    Memory device
    17.
    发明授权
    Memory device 有权

    公开(公告)号：US11699693B2

    公开(公告)日：2023-07-11

    申请号：US17545522

    申请日：2021-12-08

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Jooyong Park ,  Chanho Kim ,  Daeseok Byeon

    IPC: H01L23/00 ,  H01L25/18 ,  H01L25/065

    CPC classification number: H01L25/18 ,  H01L24/05 ,  H01L24/08 ,  H01L25/0657 ,  H01L2224/05147 ,  H01L2224/08145 ,  H01L2924/1431 ,  H01L2924/14511

    Abstract: A memory device includes first and second chips. The first chip includes a memory cell array disposed on a first substrate, and first metal pads on a first uppermost metal layer of the first chip. The second chip includes peripheral circuits disposed on a second substrate, and second metal pads on a second uppermost metal layer of the second chip, the peripheral circuits operating the memory cell array. A first metal pad and a second metal pad are connected in a first area, the first metal pads being connected to the memory cell array and the second metal pad being connected to the peripheral circuits. A further first metal pad and a further second metal pad are connected in a second area, the further first metal pad being not connected to the memory cell array and the further second metal pad being connected to the peripheral circuits.

    Integrated circuit device
    18.
    发明授权
    Integrated circuit device 有权

    公开(公告)号：US11329057B2

    公开(公告)日：2022-05-10

    申请号：US16944733

    申请日：2020-07-31

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Chanho Kim ,  Dongku Kang ,  Daeseok Byeon

    IPC: H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H01L27/112 ,  H01L27/11585 ,  H01L27/108 ,  H01L27/24

    Abstract: An integrated circuit device includes a memory including a memory cell insulation surrounding a memory stack and a memory cell interconnection unit, a peripheral circuit including a peripheral circuit region formed on a peripheral circuit board, and a peripheral circuit interconnection between the peripheral circuit region and the memory structure, a plurality of conductive bonding structures on a boundary between the memory cell interconnection and the peripheral circuit interconnection in a first region, the first region overlapping the memory stack in a vertical direction, and a through electrode penetrating one of the memory cell insulation and the peripheral circuit board and extended to a lower conductive pattern included in the peripheral circuit interconnection in a second region, the second region overlapping the memory cell insulation in the vertical direction.

    SEMICONDUCTOR DEVICE
    20.
    发明申请
    SEMICONDUCTOR DEVICE 有权

    公开(公告)号：US20220084959A1

    公开(公告)日：2022-03-17

    申请号：US17218230

    申请日：2021-03-31

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Changbum Kim ,  Sunghoon Kim ,  Daeseok Byeon

    IPC: H01L23/60 ,  H01L27/092 ,  H01L23/528

    Abstract: A semiconductor device includes a gate line extending in a first direction, parallel to an upper surface of a semiconductor substrate; a first active region including a first channel region disposed below the gate line and including a first conductivity-type impurity; a second active region disposed to be separated from the first active region in the first direction, including a second channel region disposed below the gate line, and including the first conductivity-type impurity; and a plurality of metal wirings disposed at a first height level above the semiconductor substrate, wherein at least one metal wiring, among the plurality of metal wirings, is directly electrically connected to the first active region, no metal wirings at the first height level are electrically connected to the second active region, and at least one metal wiring, among the plurality of metal wirings, is connected to receive a signal applied to the gate line.

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