公开(公告)号：US20240125841A1

公开(公告)日：2024-04-18

申请号：US18454404

申请日：2023-08-23

Applicant: Samsung Electronics Co., Ltd.

Inventor： Cheongwon Lee ,  Gyosoo Choo ,  Youngwoo Park ,  Seunghoon Lee ,  Jinwoo Choi

IPC: G01R31/26

CPC classification number: G01R31/2607

Abstract: An embodiment provides a test element group (TEG) circuit, including: a first pad configured for a test voltage to be applied; an amplifier including a first input terminal connected to the first pad, a second input terminal connected to a first terminal of a test transistor, and an output terminal electrically connected to the second input terminal; a variable resistor including one terminal connected to the output terminal of the amplifier and the other terminal connected to the first terminal of the test transistor; and a gate driving circuit that supplies a gate voltage to a gate of the test transistor.

公开(公告)号：US20240090240A1

公开(公告)日：2024-03-14

申请号：US18367704

申请日：2023-09-13

Applicant: Samsung Electronics Co., Ltd.

Inventor： TAKUYA FUTATSUYAMA ,  Daeseok Byeon ,  Gyosoo Choo

IPC: H10B80/00 ,  H01L23/00 ,  H01L25/00 ,  H01L25/065 ,  H01L25/18

CPC classification number: H10B80/00 ,  H01L24/08 ,  H01L24/80 ,  H01L25/0657 ,  H01L25/18 ,  H01L25/50 ,  H01L2224/08145 ,  H01L2224/80006 ,  H01L2224/80895 ,  H01L2224/80896 ,  H01L2924/1431 ,  H01L2924/14511

Abstract: An integrated circuit (IC) device includes a peripheral circuit structure and cell array structure. The peripheral circuit structure includes a circuit substrate, a peripheral circuit, a first insulating layer covering the circuit substrate and the peripheral circuit, and a first bonding pad. The cell array structure includes an insulating structure having first and second surfaces opposing each other, a conductive plate on the first surface, a memory cell array on the conductive plate, a second insulating layer, a second bonding pad disposed on the second insulating layer, first and second wiring lines spaced apart from each other on the second surface, a conductive via passing through the insulating structure and connecting the conductive plate to the first wiring line, and a contact structure electrically connecting the first wiring line to the second bonding pad. The first bonding pad is in contact with the second bonding pad.

公开(公告)号：US20240046994A1

公开(公告)日：2024-02-08

申请号：US18120244

申请日：2023-03-10

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Cheonan LEE ,  Kiwhan Song ,  Gyosoo Choo ,  Sukkang Sung

IPC: G11C16/14 ,  G11C16/08 ,  H10B43/27 ,  H10B43/35 ,  H10B43/40 ,  H10B41/27 ,  H10B41/35 ,  H10B41/40

CPC classification number: G11C16/14 ,  G11C16/08 ,  H10B43/27 ,  H10B43/35 ,  H10B43/40 ,  H10B41/27 ,  H10B41/35 ,  H10B41/40

Abstract: The present disclosure provides serial-gate transistors and nonvolatile memory devices including serial-gate transistors. In some embodiments, a nonvolatile memory device includes a plurality of memory blocks, a plurality of pass transistor blocks, and a plurality of gates sequentially arranged in a horizontal direction in a gate region above a semiconductor substrate. Each of the plurality of pass transistor blocks includes a plurality of serial-gate transistors configured to transfer a plurality of driving signals to a corresponding memory block of the plurality of memory blocks. Each of the plurality of serial-gate transistors includes a first source-drain region, a gate region, and a second source-drain region that are sequentially arranged in a horizontal direction at a semiconductor substrate. The plurality of gates are electrically decoupled from each other. A plurality of block selection signals respectively applied to the plurality of gates are controlled independently of each other.

公开(公告)号：US12272409B2

公开(公告)日：2025-04-08

申请号：US18176347

申请日：2023-02-28

Applicant: Samsung Electronics Co., Ltd.

Inventor： Tae-Hong Kwon ,  Kiwhan Song ,  Gyosoo Choo

IPC: G11C7/22 ,  G11C16/04 ,  G11C16/20 ,  G11C16/26

Abstract: Various example embodiments provide a flash memory device, comprising a cell string; a page buffer connected to the cell string and a bit line and configured to sense data stored in a selected memory cell by precharging a sensing node connected to the bit line; and a voltage regulator. The page buffer comprises a latch including first and second inverters coupled between a latch node and an inverted latch node; and a pull-down NMOS transistor for tripping the sensing result of the selected memory cell to the latch node. The voltage regulator adjusts a trip voltage by providing the source voltage to the pull-down NMOS transistor. The flash memory device reduce a trip voltage variation range by using only the pull-down NMOS transistor characteristics. Also, an OFF cell margin and an ON cell margin may be secured by adjusting the level of the trip voltage using the source voltage.

公开(公告)号：US20240105267A1

公开(公告)日：2024-03-28

申请号：US18201331

申请日：2023-05-24

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Inho Kang ,  Daeseok Byeon ,  Beakhyung Cho ,  Min-Hwi Kim ,  Yongsung Cho ,  Gyosoo Choo

IPC: G11C16/24 ,  G11C16/04 ,  H01L23/00 ,  H01L25/065 ,  H01L25/18 ,  H10B41/41 ,  H10B43/40 ,  H10B80/00

CPC classification number: G11C16/24 ,  G11C16/0483 ,  H01L24/08 ,  H01L25/0657 ,  H01L25/18 ,  H10B41/41 ,  H10B43/40 ,  H10B80/00 ,  H01L2224/08145 ,  H01L2924/1431 ,  H01L2924/14511

Abstract: Provided is a non-volatile memory device including a page buffer circuit having a multi-stage structure, wherein a stage of the multi-stage structure includes a high voltage region, a first low voltage region, and a second low voltage region. The high voltage region includes a first high voltage transistor connected to one of first to sixth bit lines and a second high voltage transistor connected to one of seventh to twelfth bit lines, the first low voltage region includes a first transistor connected to the first high voltage transistor, and the second low voltage region includes a second transistor connected to the second high voltage transistor. Each of the first low voltage region and the second low voltage regions has a first width corresponding to a pitch of six bit lines, and the high voltage region has a second width corresponding to a pitch of twelve bit lines.

公开(公告)号：US20240029798A1

公开(公告)日：2024-01-25

申请号：US18176347

申请日：2023-02-28

Applicant: Samsung Electronics Co., Ltd.

Inventor： Tae-Hong KWON ,  Kiwhan Song ,  Gyosoo Choo

IPC: G11C16/26 ,  G11C16/20 ,  G11C16/04

CPC classification number: G11C16/26 ,  G11C16/20 ,  G11C16/0433

Abstract: Various example embodiments provide a flash memory device, comprising a cell string having a plurality of memory cells; a page buffer connected to the cell string and a bit line and configured to sense data stored in a selected memory cell from among the plurality of memory cells by precharging a sensing node connected to the bit line; and a voltage regulator providing a source voltage to the page buffer. The page buffer comprises a latch including first and second inverters coupled between a latch node and an inverted latch node; and a pull-down NMOS transistor for tripping the sensing result of the selected memory cell to the latch node. The voltage regulator adjusts a trip voltage by providing the source voltage to the pull-down NMOS transistor. The flash memory device according to the embodiment of the present invention may reduce a trip voltage variation range by using only the pull-down NMOS transistor characteristics. Also, according to the present invention, an OFF cell margin and an ON cell margin may be sufficiently secured by adjusting the level of the trip voltage Vtrip using the source voltage Vs.