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    SUPER-HPC ERROR CORRECTION CODE
    14.
    发明申请
    SUPER-HPC ERROR CORRECTION CODE 审中-公开

    公开(公告)号：US20200295783A1

    公开(公告)日：2020-09-17

    申请号：US16352052

    申请日：2019-03-13

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Amit BERMAN ,  Ariel DOUBCHAK

    IPC: H03M13/11 ,  H03M13/15 ,  G06F11/10

    Abstract: A memory controller is configured to perform first error correcting code (ECC) encoding on a plurality of first frames of data, generate a plurality of delta syndrome units corresponding, respectively, to the plurality of first frames of data, generate a delta syndrome codeword by performing second ECC encoding on the plurality of delta syndrome units, the delta syndrome codeword including one or more redundancy data units, perform third ECC encoding on at least one second frame of data such that the encoded at least one second frame of data is a first vector of bits, and determine a second vector of bits such that, adding the second vector of bits to the first vector of bits forms a combined vector of bits which is an ECC codeword having a delta syndrome a value of which is pre-fixed based on at least one of the one or more redundancy data units.

    MEMORY SYSTEMS HAVING REDUCED MEMORY CHANNEL TRAFFIC AND METHODS FOR OPERATING THE SAME
    15.
    发明申请
    MEMORY SYSTEMS HAVING REDUCED MEMORY CHANNEL TRAFFIC AND METHODS FOR OPERATING THE SAME 审中-公开
    具有减少的存储器信道交换的存储器系统及其操作方法

    公开(公告)号：US20160321135A1

    公开(公告)日：2016-11-03

    申请号：US14699810

    申请日：2015-04-29

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Amit BERMAN ,  Uri BEITLER ,  Jun Jin KONG

    IPC: G06F11/10 ,  H03M13/00 ,  H03M13/05

    CPC classification number: G06F11/1044 ,  G06F11/1012 ,  H03M13/05 ,  H03M13/611

    Abstract: A memory device controller includes an error correction processor and a compression processor. The error correction processor is configured to obtain error location information for page data received from a source memory block over a memory channel. The compression processor is configured to compress the obtained error location information, and to output the compressed error location information to a target memory block without the page data over the same memory channel.

    Abstract translation: 存储器件控制器包括纠错处理器和压缩处理器。 错误校正处理器被配置为获得通过存储器通道从源存储器块接收的页面数据的错误位置信息。 压缩处理器被配置为压缩获得的错误位置信息，并且将压缩的错误位置信息输出到目标存储器块，而不需要通过同一存储器通道的页数据。

    HARD DECISION DECODING OF NON-VOLATILE MEMORY USING MACHINE LEARNING
    16.
    发明公开
    HARD DECISION DECODING OF NON-VOLATILE MEMORY USING MACHINE LEARNING 审中-公开

    公开(公告)号：US20230336188A1

    公开(公告)日：2023-10-19

    申请号：US17720941

    申请日：2022-04-14

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Amit BERMAN

    IPC: H03M13/11 ,  G11C7/10 ,  G06N3/063

    CPC classification number: H03M13/1108 ,  H03M13/1125 ,  G11C7/1063 ,  G11C7/1069 ,  G06N3/063

    Abstract: A memory system includes a plurality of memory cells each storing multiple bits and a memory controller having a processor. The memory controller is configured to read outputs from the memory cells in response to a read command from a host to generate first raw data of a first page and second raw data of a second page adjacent to the first page. The memory controller is further configured to perform a hard decision (HD) decoding on the first raw data to generate first decoded data. The processor is configured to apply the first decoded data and the second raw data as input features to a machine learning algorithm to generate reliability information. The memory controller is further configured to perform a HD decoding on the second raw data using the reliability information to generate second decoded data.

    MACHINE-LEARNING ERROR-CORRECTING CODE CONTROLLER
    17.
    发明申请
    MACHINE-LEARNING ERROR-CORRECTING CODE CONTROLLER 有权

    公开(公告)号：US20220116057A1

    公开(公告)日：2022-04-14

    申请号：US17495474

    申请日：2021-10-06

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Ariel DOUBCHAK ,  Dikla SHAPIRO ,  Evgeny BLAICHMAN ,  Lital COHEN ,  Amit BERMAN

    IPC: H03M13/11 ,  G06N3/10

    Abstract: A machine-learning (ML) error-correcting code (ECC) controller may include a hard-decision (HD) ECC decoder optimized for high-speed data throughput, a soft-decision (SD) ECC decoder optimized for high-correctability data throughput, and a machine-learning equalizer (MLE) configured to variably select one of the HD ECC decoder or the SD ECC decoder for data throughput. An embodiment of the ML ECC controller may provide speed-optimized HD throughput based on a linear ECC. The linear ECC may be a soft Hamming permutation code (SHPC).

    THRESHOLD ESTIMATION IN NAND FLASH DEVICES
    18.
    发明申请
    THRESHOLD ESTIMATION IN NAND FLASH DEVICES 有权

    公开(公告)号：US20210074368A1

    公开(公告)日：2021-03-11

    申请号：US16951162

    申请日：2020-11-18

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Elisha HALPERIN ,  Evgeny BLAICHMAN ,  Amit BERMAN

    IPC: G11C16/26 ,  G11C16/34 ,  G11C16/08 ,  G11C16/04

    Abstract: A method for determining an optimal threshold of a nonvolatile memory device, the method including: reading a page from a nonvolatile memory device with a default threshold and attempting to hard decode the page using the default threshold; reading the page two more times with a predetermined offset voltage when the hard decoding fails and attempting to soft decode the page using the default threshold; approximating an empirical distribution of successfully decoded bits with a Gaussian distribution for each level; finding an intersection of the Gaussian distributions; and setting the intersection as a new reading threshold and reading the page again with the new reading threshold.

    MEMORY DEVICES AND METHODS FOR OPERATING THE SAME
    20.
    发明申请
    MEMORY DEVICES AND METHODS FOR OPERATING THE SAME 审中-公开

    公开(公告)号：US20170337967A1

    公开(公告)日：2017-11-23

    申请号：US15156956

    申请日：2016-05-17

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Amit BERMAN ,  Jun Jin Kong ,  Uri Beitler

    IPC: G11C11/56

    CPC classification number: G11C11/5628 ,  G06F11/1072 ,  G11C11/5642 ,  G11C16/08 ,  G11C2211/5648

    Abstract: A memory device includes a memory including memory cells, each of the memory cells being configured to store multiple bits of data. The memory device includes a controller configured to map the levels of the memory cells to bits such that a first half of the levels have a bit with a first binary value in a desired bit position and a second half of the levels have a bit with a second binary value in the desired bit position. The first half of the levels are a first group of consecutive levels, and the second half of the levels are a second group of consecutive levels. The controller is configured to generate a distribution for writing the data to the memory cells based on the mapping, and write the data to the memory cells based on the determined distribution.

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