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    Methods of fabricating semiconductor devices
    12.
    发明授权
    Methods of fabricating semiconductor devices 有权
    制造半导体器件的方法

    公开(公告)号：US08557664B2

    公开(公告)日：2013-10-15

    申请号：US13644166

    申请日：2012-10-03

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Kwan-sik Cho ,  Kwang-youl Chun ,  Jae-man Yoon ,  Bong-soo Kim

    IPC: H01L21/336

    CPC classification number: H01L21/768

    Abstract: A method of fabricating a semiconductor device using a recess channel array is disclosed. A substrate is provided having a first region and a second region, including a first transistor in the first region including a first gate electrode partially filling a trench, and source and drain regions that are formed at both sides of the trench, and covered by a first insulating layer. A first conductive layer is formed on the substrate. A contact hole through which the drain region is exposed is formed by patterning the first conductive layer and the first insulating layer. A contact plug is formed that fills the contact hole. A bit line is formed that is electrically connected to the drain region through the contact plug, and simultaneously a second gate electrode is formed in the second region by patterning the first conductive layer.

    Abstract translation: 公开了一种使用凹槽通道阵列制造半导体器件的方法。 提供了具有第一区域和第二区域的衬底，该第一区域和第二区域包括第一区域中的第一晶体管，该第一区域包括部分地填充沟槽的第一栅电极，以及形成在沟槽两侧的源区和漏区， 第一绝缘层。 在基板上形成第一导电层。 通过图案化第一导电层和第一绝缘层来形成漏极区域露出的接触孔。 形成一个填充接触孔的接触塞。 形成通过接触插塞电连接到漏极区的位线，同时通过对第一导电层进行构图而在第二区域中形成第二栅电极。

    Semiconductor memory device
    13.
    发明授权
    Semiconductor memory device 有权

    公开(公告)号：US10978397B2

    公开(公告)日：2021-04-13

    申请号：US16707294

    申请日：2019-12-09

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Eunjung Kim ,  Hui-Jung Kim ,  Keunnam Kim ,  Daeik Kim ,  Bong-soo Kim ,  Yoosang Hwang

    IPC: H01L23/532 ,  H01L21/764 ,  H01L27/108 ,  H01L23/522 ,  H01L23/528 ,  H01L27/24

    Abstract: A semiconductor memory device includes word lines extending in a first direction on a semiconductor substrate, bit line structures crossing over the word lines and extending in a second direction intersecting the first direction, and contact pad structures between the word lines and between the bit line structures in plan view. A spacer structure extends between the bit line structures and the contact pad structures. The spacer structure includes a first air gap extending in the second direction along sidewalls of the bit line structures and a second air gap surrounding each of the contact pad structures and coupled to the first air gap.

    Semiconductor memory device
    14.
    发明授权
    Semiconductor memory device 有权

    公开(公告)号：US10535605B2

    公开(公告)日：2020-01-14

    申请号：US15782556

    申请日：2017-10-12

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Eunjung Kim ,  Hui-Jung Kim ,  Keunnam Kim ,  Daeik Kim ,  Bong-soo Kim ,  Yoosang Hwang

    IPC: H01L23/532 ,  H01L21/764 ,  H01L23/522 ,  H01L23/528 ,  H01L27/108 ,  H01L27/24

    Abstract: A semiconductor memory device includes word lines extending in a first direction on a semiconductor substrate, bit line structures crossing over the word lines and extending in a second direction intersecting the first direction, and contact pad structures between the word lines and between the bit line structures in plan view. A spacer structure extends between the bit line structures and the contact pad structures. The spacer structure includes a first air gap extending in the second direction along sidewalls of the bit line structures and a second air gap surrounding each of the contact pad structures and coupled to the first air gap.

    Semiconductor memory device
    15.
    发明授权
    Semiconductor memory device 有权

    公开(公告)号：US10510759B2

    公开(公告)日：2019-12-17

    申请号：US16004937

    申请日：2018-06-11

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Hui-jung Kim ,  Bong-soo Kim ,  Sung-hee Han ,  Yoo-sang Hwang

    IPC: H01L27/108 ,  H01L21/768 ,  H01L49/02 ,  H01L21/321 ,  H01L21/02 ,  H01L21/311

    Abstract: A semiconductor memory device according to an example embodiment of the present inventive concept may include: a plurality of lower electrodes located on a substrate and spaced apart from one another; and an etch stop pattern located on the substrate and surrounding at least a part of each of the plurality of lower electrodes, in which the etch stop pattern includes: a first etch stop pattern including carbon; and a second etch stop pattern located on the first etch stop pattern and including a material different from a material of the first etch stop pattern.

    Semiconductor device
    16.
    发明授权
    Semiconductor device 有权

    公开(公告)号：US10128252B2

    公开(公告)日：2018-11-13

    申请号：US15646540

    申请日：2017-07-11

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Ki-seok Lee ,  Dae-ik Kim ,  Yoo-sang Hwang ,  Bong-soo Kim ,  Je-min Park

    IPC: H01L27/108 ,  H01L23/528 ,  H01L29/167 ,  H01L29/36 ,  G11C11/4091 ,  G11C11/408 ,  H01L29/423

    Abstract: A semiconductor device includes a substrate including a cell active region and a peripheral active region, a direct contact arranged on a cell insulating pattern formed on the substrate and connected to the cell active region, a bit line structure including a thin conductive pattern, contacting a top surface of the direct contact and extending in one direction, and a peripheral gate structure in the peripheral active region. The peripheral gate structure include a stacked structure of a peripheral gate insulating pattern and a peripheral gate conductive pattern, the thin conductive pattern includes a first material and the peripheral gate conductive pattern include the first material, and a level of an upper surface of the thin conductive pattern is lower than a level of an upper surface of the peripheral gate conductive pattern.

    SEMICONDUCTOR MEMORY DEVICE
    18.
    发明申请
    SEMICONDUCTOR MEMORY DEVICE 审中-公开

    公开(公告)号：US20180040561A1

    公开(公告)日：2018-02-08

    申请号：US15782556

    申请日：2017-10-12

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Eunjung Kim ,  Hui-Jung Kim ,  Keunnam Kim ,  Daeik Kim ,  Bong-soo Kim ,  Yoosang Hwang

    IPC: H01L23/532 ,  H01L23/528 ,  H01L23/522 ,  H01L27/108 ,  H01L27/24

    Abstract: A semiconductor memory device includes word lines extending in a first direction on a semiconductor substrate, bit line structures crossing over the word lines and extending in a second direction intersecting the first direction, and contact pad structures between the word lines and between the bit line structures in plan view. A spacer structure extends between the bit line structures and the contact pad structures. The spacer structure includes a first air gap extending in the second direction along sidewalls of the bit line structures and a second air gap surrounding each of the contact pad structures and coupled to the first air gap.

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