公开(公告)号：US09824726B2

公开(公告)日：2017-11-21

申请号：US15164442

申请日：2016-05-25

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jung-Hoon Han ,  Dong-Wan Kim ,  Ju-Ik Lee

IPC: H01L21/00 ,  G11C5/06 ,  H01L21/764 ,  H01L27/108 ,  H01L23/528 ,  H01L23/535 ,  H01L27/105 ,  H01L23/532 ,  G11C7/18

CPC classification number: G11C5/063 ,  G11C7/18 ,  H01L21/764 ,  H01L23/528 ,  H01L23/5329 ,  H01L23/53295 ,  H01L23/535 ,  H01L27/105 ,  H01L27/10885 ,  H01L27/10888 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor device includes a bit line structure located on a semiconductor substrate, an outer bit line spacer located on a first side surface of the bit line structure, an inner bit line spacer including a first part located between the bit line structure and the outer bit line spacer and a second part located between the semiconductor substrate and the outer bit line spacer, and a block bit line spacer located between the outer bit line spacer and the second part of the inner bit line spacer. A first air-gap is defined by the outer bit line spacer, the inner bit line spacer, and the block bit line spacer.

公开(公告)号：US11075181B2

公开(公告)日：2021-07-27

申请号：US16418036

申请日：2019-05-21

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jung-Hoon Han ,  Dong-Wan Kim ,  Dongho Kim ,  Jaewon Seo

IPC: H01L23/00 ,  H01L21/66 ,  H01L21/67

Abstract: A semiconductor device includes a semiconductor substrate including a chip region and an edge region around the chip region, a lower insulating layer on the semiconductor substrate, a chip pad on the lower insulating layer on the chip region, an upper insulating layer provided on the lower insulating layer to cover the chip pad, the upper and different insulating layers including different materials, and a redistribution chip pad on the chip region and connected to the chip pad. The upper insulating layer includes a first portion on the chip region having a first thickness, a second portion on the edge region having a second thickness, and a third portion on the edge region, the third portion extending from the second portion, spaced from the first portion, and having a decreasing thickness away from the second portion. The second thickness is smaller than the first thickness.

公开(公告)号：US09761591B2

公开(公告)日：2017-09-12

申请号：US15148405

申请日：2016-05-06

Applicant: Samsung Electronics Co., Ltd.

Inventor： Eunjung Kim ,  Sohyun Park ,  Bong-Soo Kim ,  Yoosang Hwang ,  Dong-Wan Kim ,  Junghoon Han

IPC: H01L21/20 ,  H01L27/108 ,  H01L21/56 ,  H01L21/311 ,  H01L49/02 ,  H01L21/3105 ,  H01L21/027

CPC classification number: H01L27/10894 ,  H01L21/0274 ,  H01L21/31051 ,  H01L21/31144 ,  H01L21/565 ,  H01L27/10814 ,  H01L27/10823 ,  H01L27/10852 ,  H01L27/10897 ,  H01L27/11582 ,  H01L28/00 ,  H01L28/60

Abstract: A method of forming a semiconductor device includes forming a molding layer and a supporter layer on a substrate including an etch stop layer, forming a mask layer on the supporter layer, forming a first edge blocking layer on the mask layer, forming a mask pattern by etching the mask layer, forming a hole, forming a lower electrode in the hole, forming a supporter mask layer on the supporter layer, forming a second edge blocking layer on the supporter mask layer, forming a supporter mask pattern by patterning the supporter mask layer, forming a supporter opening passing through the supporter layer, removing the molding layer, forming a capacitor dielectric layer and an upper electrode on the lower electrode, forming an interlayer insulating layer on the upper electrode, and planarizing the interlayer insulating layer. The hole passes through the supporter layer, the molding layer and the etch stop layer.

公开(公告)号：US20170025416A1

公开(公告)日：2017-01-26

申请号：US15067705

申请日：2016-03-11

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jung-Hoon Han ,  Jong-Min Lee ,  Dong-Wan Kim ,  Ju-Ik Lee

IPC: H01L27/108 ,  H01L29/423 ,  H01L49/02

CPC classification number: H01L27/10814 ,  H01L27/10823 ,  H01L27/10855 ,  H01L27/10876 ,  H01L28/60 ,  H01L28/86 ,  H01L29/4236

Abstract: A capacitor structure includes a plurality of lower electrodes, a support pattern structure, a dielectric layer, and an upper electrode. The lower electrodes are formed on a substrate. The support pattern structure is formed between the lower electrodes, and includes a lower support pattern and an upper support pattern structure over the lower support pattern. The upper support pattern structure includes a plurality of upper support patterns spaced apart from each other in a direction substantially perpendicular to a top surface of the substrate. The dielectric layer is formed on the lower electrodes and the support pattern structure. The upper electrode is formed on the dielectric layer. A sum of thicknesses of the plurality of upper support patterns in the direction substantially perpendicular to the top surface of the substrate is about 35% to about 85% of a total thickness of the upper support pattern structure.

Abstract translation: 电容器结构包括多个下电极，支撑图案结构，电介质层和上电极。 下电极形成在基板上。 支撑图案结构形成在下电极之间，并且在下支撑图案上方包括下支撑图案和上支撑图案结构。 上支撑图案结构包括在基本上垂直于基板的顶表面的方向上彼此间隔开的多个上支撑图案。 电介质层形成在下电极和支撑图案结构上。 上电极形成在电介质层上。 多个上支撑图案在基本上垂直于基板顶表面的方向上的厚度之和为上支撑图案结构的总厚度的约35％至约85％。

公开(公告)号：US09379002B2

公开(公告)日：2016-06-28

申请号：US14554113

申请日：2014-11-26

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jung-Hoon Han ,  Dong-Wan Kim ,  Ju-Ik Lee

IPC: H01L21/00 ,  H01L21/764 ,  H01L27/108 ,  H01L23/532 ,  G11C7/18

CPC classification number: G11C5/063 ,  G11C7/18 ,  H01L21/764 ,  H01L23/528 ,  H01L23/5329 ,  H01L23/53295 ,  H01L23/535 ,  H01L27/105 ,  H01L27/10885 ,  H01L27/10888 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor device includes a bit line structure located on a semiconductor substrate, an outer bit line spacer located on a first side surface of the bit line structure, an inner bit line spacer including a first part located between the bit line structure and the outer bit line spacer and a second part located between the semiconductor substrate and the outer bit line spacer, and a block bit line spacer located between the outer bit line spacer and the second part of the inner bit line spacer. A first air-gap is defined by the outer bit line spacer, the inner bit line spacer, and the block bit line spacer.

Abstract translation: 半导体器件包括位于半导体衬底上的位线结构，位线在位线结构的第一侧表面上的外部位线间隔件，内部位线间隔件包括位于位线结构和外部位之间的第一部分 并且位于半导体衬底和外部位线间隔物之间​​的第二部分和位于外部位线间隔物和内部位线间隔物的第二部分之间的块位线间隔件。 第一气隙由外部位线间隔件，内部位线间隔件和块位线间隔件限定。

公开(公告)号：US11626377B2

公开(公告)日：2023-04-11

申请号：US17361588

申请日：2021-06-29

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jung-Hoon Han ,  Dong-Wan Kim ,  Dongho Kim ,  Jaewon Seo

IPC: H01L23/00 ,  H01L21/66 ,  H01L21/67

Abstract: A semiconductor device includes a semiconductor substrate including a chip region and an edge region around the chip region, a lower insulating layer on the semiconductor substrate, a chip pad on the lower insulating layer on the chip region, an upper insulating layer provided on the lower insulating layer to cover the chip pad, the upper and different insulating layers including different materials, and a redistribution chip pad on the chip region and connected to the chip pad. The upper insulating layer includes a first portion on the chip region having a first thickness, a second portion on the edge region having a second thickness, and a third portion on the edge region, the third portion extending from the second portion, spaced from the first portion, and having a decreasing thickness away from the second portion. The second thickness is smaller than the first thickness.

公开(公告)号：US20230045674A1

公开(公告)日：2023-02-09

申请号：US17662306

申请日：2022-05-06

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyeon-Woo Jang ,  Dong-Wan Kim ,  Keonhee Park ,  Dong-Sik Park ,  Joonsuk Park ,  Jihoon Chang

IPC: H01L27/108

Abstract: A semiconductor device may include a substrate including a cell region and a peripheral region, a gate stack on the peripheral region, an interlayer insulating layer on the gate stack, peripheral circuit interconnection lines on the interlayer insulating layer, and an interconnection insulating pattern between the peripheral circuit interconnection lines. The interconnection insulating pattern may include a pair of vertical portions spaced apart from each other in a first direction parallel to a top surface of the substrate and a connecting portion connecting the vertical portions to each other. Each of the vertical portions of the interconnection insulating pattern may have a first thickness at a same level as top surfaces of the peripheral circuit interconnection lines and a second thickness at a same level as bottom surfaces of the peripheral circuit interconnection lines. The first thickness may be substantially equal to the second thickness.

公开(公告)号：US11075183B2

公开(公告)日：2021-07-27

申请号：US16455788

申请日：2019-06-28

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ju-Ik Lee ,  Dong-Wan Kim ,  Seokho Shin ,  Jung-Hoon Han ,  Sang-Oh Park

IPC: H01L23/48 ,  H01L23/00 ,  H01L25/18 ,  H01L23/528 ,  H01L23/31 ,  H01L23/522

Abstract: A semiconductor device includes a semiconductor substrate and a connection terminal, including a base pillar, on the semiconductor substrate. An insulation layer is formed on the semiconductor substrate, the insulation layer including an opening in the insulation layer through which the base pillar extends, wherein a side wall of the insulation layer defining the opening includes a horizontal step at a level that is lower than an uppermost portion of the base pillar.

公开(公告)号：US10950523B2

公开(公告)日：2021-03-16

申请号：US16426612

申请日：2019-05-30

Applicant: Samsung Electronics Co., Ltd.

Inventor： Dong-Wan Kim ,  Jung-Hoon Han ,  Dong-Sik Park

IPC: H01L23/48 ,  H01L23/538 ,  H01L21/768

Abstract: The semiconductor device includes a substrate including an integrated circuit and a contact that are electrically connected to each other, an insulation layer covering the substrate and including metal lines, and a through electrode electrically connected to the integrated circuit. The insulation layer includes an interlayer dielectric layer on the substrate and an intermetal dielectric layer on the interlayer dielectric layer. The metal lines include a first metal line in the interlayer dielectric layer and electrically connected to the contact, and a plurality of second metal lines in the intermetal dielectric layer and electrically connected to the first metal line and the through electrode. The through electrode includes a top surface higher than a top surface of the contact.

公开(公告)号：US10600791B2

公开(公告)日：2020-03-24

申请号：US16125167

申请日：2018-09-07

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Dong-Wan Kim ,  Keunnam Kim ,  Juik Lee

IPC: H01L27/108 ,  H01L27/22 ,  G11C8/08 ,  H01L23/535 ,  H01L27/24 ,  G11C8/14

Abstract: A semiconductor memory device includes a word line buried in an upper portion of a substrate and extending in a first direction, and a word line contact plug connected to the word line. An end portion of the word line includes a contact surface exposed in the first direction, and the word line contact plug is connected to the contact surface.