公开(公告)号：US09991203B2

公开(公告)日：2018-06-05

申请号：US15298855

申请日：2016-10-20

Applicant: Samsung Electronics Co., Ltd.

Inventor： Rak-Hwan Kim ,  Byung-Hee Kim ,  Jin-Nam Kim ,  Jong-Min Baek ,  Nae-In Lee ,  Eun-Ji Jung

IPC: H01L29/40 ,  H01L21/44 ,  H01L23/528 ,  H01L21/768 ,  H01L23/532

CPC classification number: H01L23/5283 ,  H01L21/76847 ,  H01L21/76877 ,  H01L23/53209 ,  H01L23/53238 ,  H01L23/53261 ,  H01L23/53266

Abstract: A semiconductor device and a method of fabricating the same are provided. The semiconductor device includes an interlayer insulating film, a first trench having a first width, and a second trench having a second width, the second trench including an upper portion and a lower portion, the second width being greater than the first width, a first wire substantially filling the first trench and including a first metal, and a second wire substantially filling the second trench and including a lower wire and an upper wire, the lower wire substantially filling a lower portion of the second trench and including the first metal, and the upper wire substantially filling an upper portion of the second trench and including a second metal different from the first metal.

公开(公告)号：US09773699B2

公开(公告)日：2017-09-26

申请号：US15000302

申请日：2016-01-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jong-Jin Lee ,  Rak-Hwan Kim ,  Byung-Hee Kim ,  Jin-Nam Kim ,  Tsukasa Matsuda ,  Wan-Soo Park ,  Nae-In Lee ,  Jae-Won Chang ,  Eun-Ji Jung ,  Jeong-Ok Cha ,  Jae-Won Hwang ,  Jung-Ha Hwang

IPC: H01L21/76 ,  H01L21/768 ,  H01L23/522 ,  H01L23/528 ,  H01L23/532

CPC classification number: H01L21/76882 ,  H01L21/76807 ,  H01L21/76843 ,  H01L21/76864 ,  H01L21/76877 ,  H01L23/522 ,  H01L23/5226 ,  H01L23/5283 ,  H01L23/53238

Abstract: In a method of forming a wiring structure, a lower structure is formed on a substrate. An insulating interlayer is formed on the lower structure. The insulating interlayer is partially removed to form at least one via hole and a dummy via hole. An upper portion of the insulating interlayer is partially removed to form a trench connecting the via hole and the dummy via hole. A first metal layer filling the via hole and the dummy via hole is formed. A second metal layer filling the trench is formed on the first metal layer.

公开(公告)号：US20230170252A1

公开(公告)日：2023-06-01

申请号：US17933216

申请日：2022-09-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jong Jin Lee ,  Seung Yong Yoo ,  Eun-Ji Jung

IPC: H01L21/768 ,  H01L23/522 ,  H01L23/532 ,  H01L29/49

CPC classification number: H01L21/76811 ,  H01L21/76877 ,  H01L23/5226 ,  H01L23/53266 ,  H01L29/4983

Abstract: The present disclosure provides a semiconductor device capable of improving element performance and reliability. The semiconductor device comprises a lower wiring structure, an upper interlayer insulating layer disposed on the lower wiring structure and including an upper wiring trench, the upper wiring trench exposing a portion of the lower wiring structure, and an upper wiring structure including an upper liner and an upper filling layer on the upper liner in the upper wiring trench, wherein the upper liner includes a sidewall portion extending along a sidewall of the upper wiring trench and a bottom portion extending along a bottom surface of the upper wiring trench, the sidewall portion of the upper liner includes cobalt (Co) and ruthenium (Ru), and the bottom portion of the upper liner is formed of cobalt (Co).

公开(公告)号：US20230064127A1

公开(公告)日：2023-03-02

申请号：US18053487

申请日：2022-11-08

Applicant: Samsung Electronics Co., Ltd.

Inventor： JONGJIN LEE ,  Kyungwook Kim ,  Rakhwan Kim ,  Seungyong Yoo ,  Eun-Ji Jung

IPC: H01L23/522 ,  H01L23/532 ,  H01L29/45

Abstract: Semiconductor devices includes a first interlayer insulating layer, a lower interconnection line in the first interlayer insulating layer, an etch stop layer on the first interlayer insulating layer and the lower interconnection line, a second interlayer insulating layer on the etch stop layer, and an upper interconnection line in the second interlayer insulating layer. The upper interconnection line includes a via portion extending through the etch stop layer and contacting the lower interconnection line. The via portion includes a barrier pattern and a conductive pattern. The barrier pattern includes a first barrier layer between the conductive pattern and the second interlayer insulating layer, and a second barrier layer between the conductive pattern and the lower interconnection line. A resistivity of the first barrier layer is greater than that of the second barrier layer. A nitrogen concentration of the first barrier layer is greater than that of the second barrier layer.

公开(公告)号：US20210090999A1

公开(公告)日：2021-03-25

申请号：US16892649

申请日：2020-06-04

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Seung Yong YOO ,  Jong Jin Lee ,  Rak Hwan Kim ,  Eun-Ji Jung ,  Won Hyuk Hong

IPC: H01L23/528 ,  H01L21/768 ,  H01L21/285 ,  H01L23/532 ,  H01L23/522

Abstract: A semiconductor device includes a first interlayer insulating film disposed on a substrate and having a first trench. A first lower conductive pattern fills the first trench and includes first and second valley areas that are spaced apart from each other in a first direction parallel to an upper surface of the substrate. The first and second valley areas are recessed toward the substrate. A second interlayer insulating film is disposed on the first interlayer insulating film and includes a second trench that exposes at least a portion of the first lower conductive pattern. An upper conductive pattern fills the second trench and includes an upper barrier film and an upper filling film disposed on the upper barrier film. The upper conductive pattern at least partially fills the first valley area.

公开(公告)号：US10700164B2

公开(公告)日：2020-06-30

申请号：US16274350

申请日：2019-02-13

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jin-Nam Kim ,  Rak-Hwan Kim ,  Byung-Hee Kim ,  Jong-Min Baek ,  Sang-Hoon Ahn ,  Nae-In Lee ,  Jong-Jin Lee ,  Ho-Yun Jeon ,  Eun-Ji Jung

IPC: H01L29/08 ,  H01L23/532 ,  H01L21/768 ,  H01L23/522 ,  H01L23/528 ,  H01L27/088 ,  H01L27/12

Abstract: Semiconductor devices may include a diffusion prevention insulation pattern, a plurality of conductive patterns, a barrier layer, and an insulating interlayer. The diffusion prevention insulation pattern may be formed on a substrate, and may include a plurality of protrusions protruding upwardly therefrom. Each of the conductive patterns may be formed on each of the protrusions of the diffusion prevention insulation pattern, and may have a sidewall inclined by an angle in a range of about 80 degrees to about 135 degrees to a top surface of the substrate. The barrier layer may cover a top surface and the sidewall of each if the conductive patterns. The insulating interlayer may be formed on the diffusion prevention insulation pattern and the barrier layer, and may have an air gap between neighboring ones of the conductive patterns.

公开(公告)号：US20170294337A1

公开(公告)日：2017-10-12

申请号：US15632884

申请日：2017-06-26

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jin-Nam KIM ,  Rak-Hwan Kim ,  Byung-Hee Kim ,  Jong-Min Baek ,  Sang-Hoon Ahn ,  Nae-In Lee ,  Jong-Jin Lee ,  Ho-Yun Jeon ,  Eun-Ji Jung

IPC: H01L21/768 ,  H01L23/528 ,  H01L23/532

CPC classification number: H01L29/0847 ,  H01L21/7682 ,  H01L21/76834 ,  H01L21/76837 ,  H01L21/76852 ,  H01L21/76862 ,  H01L21/76885 ,  H01L23/5222 ,  H01L23/5283 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/53266 ,  H01L23/53295 ,  H01L27/0886 ,  H01L27/1211

Abstract: Semiconductor devices may include a diffusion prevention insulation pattern, a plurality of conductive patterns, a barrier layer, and an insulating interlayer. The diffusion prevention insulation pattern may be formed on a substrate, and may include a plurality of protrusions protruding upwardly therefrom. Each of the conductive patterns may be formed on each of the protrusions of the diffusion prevention insulation pattern, and may have a sidewall inclined by an angle in a range of about 80 degrees to about 135 degrees to a top surface of the substrate. The barrier layer may cover a top surface and the sidewall of each if the conductive patterns. The insulating interlayer may be formed on the diffusion prevention insulation pattern and the barrier layer, and may have an air gap between neighboring ones of the conductive patterns.

公开(公告)号：US20160300792A1

公开(公告)日：2016-10-13

申请号：US15059438

申请日：2016-03-03

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jin-Nam KIM ,  Rak-Hwan Kim ,  Byung-Hee Kim ,  Jong-Min Baek ,  Sang-Hoon Ahn ,  Nae-In Lee ,  Jong-Jin Lee ,  Ho-Yun Jeon ,  Eun-Ji Jung

IPC: H01L23/528 ,  H01L29/78 ,  H01L29/08 ,  H01L29/51 ,  H01L29/16 ,  H01L29/161 ,  H01L23/532 ,  H01L29/06

CPC classification number: H01L29/0847 ,  H01L21/7682 ,  H01L21/76834 ,  H01L21/76837 ,  H01L21/76852 ,  H01L21/76862 ,  H01L21/76885 ,  H01L23/5222 ,  H01L23/5283 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/53266 ,  H01L23/53295 ,  H01L27/0886 ,  H01L27/1211

Abstract: Semiconductor devices may include a diffusion prevention insulation pattern, a plurality of conductive patterns, a barrier layer, and an insulating interlayer. The diffusion prevention insulation pattern may be formed on a substrate, and may include a plurality of protrusions protruding upwardly therefrom. Each of the conductive patterns may be formed on each of the protrusions of the diffusion prevention insulation pattern, and may have a sidewall inclined by an angle in a range of about 80 degrees to about 135 degrees to a top surface of the substrate. The barrier layer may cover a top surface and the sidewall of each if the conductive patterns. The insulating interlayer may be formed on the diffusion prevention insulation pattern and the barrier layer, and may have an air gap between neighboring ones of the conductive patterns.

Abstract translation: 半导体器件可以包括扩散防止绝缘图案，多个导电图案，阻挡层和绝缘中间层。 扩散防止绝缘图案可以形成在基板上，并且可以包括从其向上突出的多个突起。 每个导电图案可以形成在防扩散绝缘图案的每个突起上，并且可以具有相对于基板的顶表面倾斜约80度至约135度范围内的角度的侧壁。 如果导电图案，阻挡层可以覆盖每个的顶表面和侧壁。 绝缘中间层可以形成在防扩散绝缘图案和阻挡层上，并且可以在相邻的导电图案之间具有气隙。

公开(公告)号：US20170133317A1

公开(公告)日：2017-05-11

申请号：US15298855

申请日：2016-10-20

Applicant: Samsung Electronics Co., Ltd.

Inventor： Rak-Hwan KIM ,  Byung-Hee Kim ,  Jin-Nam Kim ,  Jong-Min Baek ,  Nae-In Lee ,  Eun-Ji Jung

IPC: H01L23/528 ,  H01L23/532 ,  H01L21/768 ,  H01L23/522

CPC classification number: H01L23/5283 ,  H01L21/76847 ,  H01L21/76877 ,  H01L23/53209 ,  H01L23/53238 ,  H01L23/53261 ,  H01L23/53266

Abstract: A semiconductor device and a method of fabricating the same are provided. The semiconductor device includes an interlayer insulating film, a first trench having a first width, and a second trench having a second width, the second trench including an upper portion and a lower portion, the second width being greater than the first width, a first wire substantially filling the first trench and including a first metal, and a second wire substantially filling the second trench and including a lower wire and an upper wire, the lower wire substantially filling a lower portion of the second trench and including the first metal, and the upper wire substantially filling an upper portion of the second trench and including a second metal different from the first metal.