公开(公告)号：US11133383B2

公开(公告)日：2021-09-28

申请号：US16741868

申请日：2020-01-14

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Chang Woo Noh ,  Dong Il Bae ,  Geum Jong Bae

IPC: H01L29/06 ,  H01L21/02 ,  H01L21/311 ,  H01L21/84 ,  H01L27/12 ,  H01L29/08 ,  H01L29/10 ,  H01L29/165 ,  H01L29/423 ,  H01L29/66

Abstract: A semiconductor device including a buried insulating layer on a substrate; a lower semiconductor layer on the buried insulating layer, the lower semiconductor layer including a first material; a channel pattern on the lower semiconductor layer, the channel pattern being spaced apart from the lower semiconductor layer and including a second material different from the first material; and a gate electrode surrounding at least a portion of the channel pattern.

公开(公告)号：US11024628B2

公开(公告)日：2021-06-01

申请号：US16405174

申请日：2019-05-07

Applicant: Samsung Electronics Co., Ltd.

Inventor： Chang Woo Noh ,  Myung Gil Kang ,  Geum Jong Bae ,  Dong Il Bae ,  Jung Gil Yang ,  Sang Hoon Lee

IPC: H01L27/092 ,  H01L29/78 ,  H01L29/66 ,  H01L21/033 ,  H01L21/8238 ,  H01L29/10 ,  H01L29/08

Abstract: Semiconductor devices are provided. The semiconductor devices may include a first wire pattern extending in a first direction on a substrate and a second wire pattern on the first wire pattern. The second wire pattern may be spaced apart from the first wire pattern and extends in the first direction. The semiconductor devices may also include a first gate structure at least partially surrounding the first wire pattern and the second wire pattern, a second gate structure spaced apart from the first gate structure in the first direction, a first source/drain region between the first gate structure and the second gate structure, a first spacer between a bottom surface of the first source/drain region and the substrate, a first source/drain contact on the first source/drain region, and a second spacer between the first source/drain contact and the first gate structure.

公开(公告)号：US10181510B2

公开(公告)日：2019-01-15

申请号：US15726535

申请日：2017-10-06

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jung Gil Yang ,  Seung Min Song ,  Sung Min Kim ,  Woo Seok Park ,  Geum Jong Bae ,  Dong Il Bae

IPC: H01L29/76 ,  H01L29/06 ,  H01L29/49 ,  H01L29/66 ,  H01L29/786

Abstract: A method of manufacturing a semiconductor device is provided. A stacked structure including one or more sacrificial layers and one or more semiconductor layers are stacked on a substrate is formed. A dummy gate structure including a dummy gate and a dummy spacer on the stacked structure is formed. The stacked structure is etched using the dummy gate structure to form a first recess. The one or more sacrificial layers are etched. The dummy spacer is removed. A spacer film is formed on the dummy gate, the one or more semiconductor layer and the one or more sacrificial layers. The semiconductor layer and spacer film are etched to form a second recess using the dummy gate and spacer film. An external spacer formed on the dummy gate and an internal spacer formed on the one or more sacrificial layers are formed. A source/drain region is formed in the second recess.

公开(公告)号：US20180212067A1

公开(公告)日：2018-07-26

申请号：US15933505

申请日：2018-03-23

Applicant: Samsung Electronics Co, Ltd

Inventor： Jong Ho LEE ,  Ho Jun Kim ,  Sung Dae Suk ,  Geum Jong Bae

IPC: H01L29/786 ,  H01L29/423 ,  H01L29/06

Abstract: A semiconductor device according to example embodiments of inventive concepts may include a substrate, source/drain regions extending perpendicular to an upper surface of the substrate, a plurality of nanosheets on the substrate and separated from each other, and a gate electrode and a gate insulating layer on the substrate. The nanosheets define channel regions that extend in a first direction between the source/drain regions. The gate electrode surrounds the nanosheets and extends in a second direction intersecting the first direction. The gate insulating layer is between the nanosheets and the gate electrode. A length of the gate electrode in the first direction may be greater than a space between adjacent nanosheets among the nanosheets.

公开(公告)号：US11710741B2

公开(公告)日：2023-07-25

申请号：US17243943

申请日：2021-04-29

Applicant: Samsung Electronics Co., Ltd.

Inventor： Chang Woo Noh ,  Myung Gil Kang ,  Geum Jong Bae ,  Dong Il Bae ,  Jung Gil Yang ,  Sang Hoon Lee

IPC: H01L27/092 ,  H01L29/78 ,  H01L29/66 ,  H01L21/033 ,  H01L21/8238 ,  H01L29/10 ,  H01L29/08

CPC classification number: H01L27/0924 ,  H01L21/0337 ,  H01L21/823821 ,  H01L21/823828 ,  H01L21/823864 ,  H01L21/823871 ,  H01L29/0847 ,  H01L29/1033 ,  H01L29/6656 ,  H01L29/6681 ,  H01L29/66545 ,  H01L29/785 ,  H01L2029/7858

Abstract: Semiconductor devices are provided. The semiconductor devices may include a first wire pattern extending in a first direction on a substrate and a second wire pattern on the first wire pattern. The second wire pattern may be spaced apart from the first wire pattern and extends in the first direction. The semiconductor devices may also include a first gate structure at least partially surrounding the first wire pattern and the second wire pattern, a second gate structure spaced apart from the first gate structure in the first direction, a first source/drain region between the first gate structure and the second gate structure, a first spacer between a bottom surface of the first source/drain region and the substrate, a first source/drain contact on the first source/drain region, and a second spacer between the first source/drain contact and the first gate structure.

公开(公告)号：US11069818B2

公开(公告)日：2021-07-20

申请号：US16435657

申请日：2019-06-10

Applicant: Samsung Electronics Co., Ltd.

Inventor： Myung Gil Kang ,  Dong Won Kim ,  Geum Jong Bae ,  Kwan Young Chun

IPC: H01L29/786 ,  H01L27/092 ,  H01L27/11 ,  H01L29/423 ,  H01L29/06

Abstract: A semiconductor device is provided. The semiconductor device includes: a first wire pattern disposed on a substrate and extending in a first direction; a first gate electrode surrounding the first wire pattern and extending in a second direction, the first direction intersecting the second direction perpendicularly; a first transistor including the first wire pattern and the first gate electrode; a second wire pattern disposed on the substrate and extending in the first direction; a second gate electrode surrounding the second wire pattern and extending in the second direction; and a second transistor including the second wire pattern and the second gate electrode, wherein a width of the first wire pattern in the second direction is different from a width of the second wire pattern in the second direction.

公开(公告)号：US10818802B2

公开(公告)日：2020-10-27

申请号：US15933505

申请日：2018-03-23

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jong Ho Lee ,  Ho Jun Kim ,  Sung Dae Suk ,  Geum Jong Bae

IPC: H01L29/786 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66

Abstract: A semiconductor device according to example embodiments of inventive concepts may include a substrate, source/drain regions extending perpendicular to an upper surface of the substrate, a plurality of nanosheets on the substrate and separated from each other, and a gate electrode and a gate insulating layer on the substrate. The nanosheets define channel regions that extend in a first direction between the source/drain regions. The gate electrode surrounds the nanosheets and extends in a second direction intersecting the first direction. The gate insulating layer is between the nanosheets and the gate electrode. A length of the gate electrode in the first direction may be greater than a space between adjacent nanosheets among the nanosheets.

公开(公告)号：US20200091152A1

公开(公告)日：2020-03-19

申请号：US16405174

申请日：2019-05-07

Applicant: Samsung Electronics Co., Ltd.

Inventor： Chang Woo Noh ,  Myung Gil Kang ,  Geum Jong Bae ,  Dong Il Bae ,  Jung Gil Yang ,  Sang Hoon Lee

IPC: H01L27/092 ,  H01L29/78 ,  H01L29/66 ,  H01L21/033 ,  H01L21/8238 ,  H01L29/10 ,  H01L29/08

Abstract: Semiconductor devices are provided. The semiconductor devices may include a first wire pattern extending in a first direction on a substrate and a second wire pattern on the first wire pattern. The second wire pattern may be spaced apart from the first wire pattern and extends in the first direction. The semiconductor devices may also include a first gate structure at least partially surrounding the first wire pattern and the second wire pattern, a second gate structure spaced apart from the first gate structure in the first direction, a first source/drain region between the first gate structure and the second gate structure, a first spacer between a bottom surface of the first source/drain region and the substrate, a first source/drain contact on the first source/drain region, and a second spacer between the first source/drain contact and the first gate structure.

公开(公告)号：US20190393315A1

公开(公告)日：2019-12-26

申请号：US16205851

申请日：2018-11-30

Applicant: Samsung Electronics Co., Ltd.

Inventor： Chang Woo NOH ,  Seung Min Song ,  Geum Jong Bae ,  Dong Il Bae

IPC: H01L29/417 ,  H01L29/66 ,  H01L29/78 ,  H01L21/768 ,  H01L29/06

Abstract: A semiconductor device including a fin field effect transistor (fin-FET) includes active fins disposed on a substrate, isolation layers on both sides of the active fins, a gate structure formed to cross the active fins and the isolation layers, source/drain regions on the active fins on sidewalls of the gate structure, a first interlayer insulating layer on the isolation layers in contact with portions of the sidewalls of the gate structure and portions of surfaces of the source/drain regions, an etch stop layer configured to overlap the first interlayer insulating layer, the sidewalls of the gate structure, and the source/drain regions, and contact plugs formed to pass through the etch stop layer to contact the source/drain regions. The source/drain regions have main growth portions in contact with upper surfaces of the active fins.

公开(公告)号：US10204983B2

公开(公告)日：2019-02-12

申请号：US15444550

申请日：2017-02-28

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sung Dae Suk ,  Seung Min Song ,  Geum Jong Bae

IPC: H01L29/06 ,  H01L29/423 ,  H01L29/49 ,  H01L29/51 ,  H01L29/66 ,  H01L29/78 ,  H01L29/786 ,  H01L29/775

Abstract: A semiconductor device may include a substrate, a first nanowire, a gate electrode, a first gate spacer, a second gate spacer, a source/drain and a spacer connector. The first nanowire may be extended in a first direction and spaced apart from the substrate. The gate electrode may surround a periphery of the first nanowire, and extend in a second direction intersecting the first direction, and include first and second sidewalls opposite to each other. The first gate spacer may be formed on the first sidewall of the gate electrode. The first nanowire may pass through the first gate spacer. The second gate spacer may be formed on the second sidewall of the gate electrode. The first nanowire may pass through the second gate spacer. The source/drain may be disposed on at least one side of the gate electrode and connected with the first nanowire. The spacer connector may be disposed between the first nanowire and the substrate. The spacer connector may connect the first gate spacer and the second gate spacer to each other.