MEMORY DEVICE AND OPERATION METHOD THEREOF

    公开(公告)号:US20230138601A1

    公开(公告)日:2023-05-04

    申请号:US17957532

    申请日:2022-09-30

    Abstract: Disclosed is a memory device includes a memory block that is connected with a plurality of wordlines, a voltage generating circuit configured to output a first non-selection voltage through a plurality of driving lines, and an address decoding circuit configured to connect the plurality of driving lines with unselected wordlines of the plurality of wordlines. During a wordline setup period for the plurality of wordlines, the voltage generating circuit floats first driving lines corresponding to first unselected wordlines of the unselected wordlines from among the plurality of driving lines when the first unselected wordlines reach a first target level, and floats second driving lines corresponding to second unselected wordlines of the unselected wordlines from among the plurality of driving lines when the second unselected wordlines reach a second target level different from the first target level.

    NON-VOLATILE MEMORY DEVICE AND METHOD FOR PROGRAMMING A NON-VOLATILE MEMORY DEVICE

    公开(公告)号:US20220157393A1

    公开(公告)日:2022-05-19

    申请号:US17530586

    申请日:2021-11-19

    Abstract: A method for programming at least one memory cell of a plurality of memory cells included in a non-volatile memory device, the at least one memory cell including a word line and a bit line, the method including: performing a first and second program and verify operation based on a first and second condition, respectively, wherein each program and verify operation includes generating a program voltage and a bit line voltage by a voltage generator included in the non-volatile memory device and providing the program voltage and the bit line voltage to the word line and the bit line, respectively, wherein voltage levels and voltage application times of each program voltage and bit line voltage correspond to the first condition or the second condition, respectively, wherein the first condition is different from the second condition.

    NEGATIVE LEVEL SHIFTERS AND NONVOLATILE MEMORY DEVICES INCLUDING THE SAME

    公开(公告)号:US20220084600A1

    公开(公告)日:2022-03-17

    申请号:US17220368

    申请日:2021-04-01

    Abstract: A negative level shifter includes a shifting circuit and a latch circuit. The shifting circuit shifts levels of a first input signal and a second input signal to provide a first output signal and a second output signal having complementary levels at a first output node and a second output node, respectively, using low voltage transistors and high voltage transistors having different characteristics. The latch circuit, connected to the shifting circuit at the first output node and the second output node, latches the first output signal and the second output signal, receives a negative voltage having a level smaller than a ground voltage, and drives the second output signal and the first output signal complementarily to either a level of a power supply voltage or a level of the negative voltage, based on voltage levels at the first output node and the second output node, respectively.

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