公开(公告)号：US11581331B2

公开(公告)日：2023-02-14

申请号：US17101401

申请日：2020-11-23

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hyo Joon Ryu ,  Young Hwan Son ,  Seo-Goo Kang ,  Jung Hoon Jun ,  Kohji Kanamori ,  Jee Hoon Han

IPC: H01L27/11582 ,  H01L23/535 ,  H01L27/11573 ,  H01L27/11529 ,  H01L27/11556

Abstract: A semiconductor memory includes metallic lines on a substrate and including an uppermost metallic line, a semiconductor conduction line on the uppermost metallic line, a vertical structure penetrating the semiconductor conduction line and metallic lines, and including a vertical structure that includes an upper channel film, a first lower channel film, and an upper connection channel film connecting the upper channel film and the first lower channel film between a bottom of the semiconductor conduction line and a bottom of the uppermost metallic line, and a first cutting line through the metallic lines and the semiconductor conduction line, and including a first upper cutting line through the semiconductor conduction line, and a first lower cutting line through the plurality of metallic lines, a width of the first upper cutting line being greater than a width of an extension line of a sidewall of the first lower cutting line.

公开(公告)号：US20220037316A1

公开(公告)日：2022-02-03

申请号：US17334589

申请日：2021-05-28

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： SEUNG YOON KIM ,  Jae Ryong Sim ,  Jee Hoon Han

IPC: H01L27/088 ,  H01L29/417 ,  H01L21/8234

Abstract: A semiconductor device includes an active region that extends in a first direction and has a first width in a second direction that intersects the first direction, a first gate structure disposed on the active region that has a second width in the first direction and extends in the second direction, a first metal contact spaced apart from the first gate structure in the first direction, a first trench formed in the active region, and an insulating material that fills the first trench and forms a first active cut, wherein the first active cut defines a first metal region in the active region in which the first metal contact is located, and the first metal contact is placed off-center inside the first metal region and a length of a region where the first gate structure and the active region overlap is greater than that of the first and second trenches.

公开(公告)号：US11227870B2

公开(公告)日：2022-01-18

申请号：US16739392

申请日：2020-01-10

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Joo-Heon Kang ,  Tae Hun Kim ,  Jae Ryong Sim ,  Kwang Young Jung ,  Gi Yong Chung ,  Jee Hoon Han ,  Doo Hee Hwang

IPC: H01L27/11578 ,  H01L27/11582 ,  H01L27/1157

Abstract: A semiconductor memory device includes a third insulating pattern and a first insulating pattern on a substrate, the third insulating pattern and the first insulating pattern being spaced apart from each other in a first direction that is perpendicular to the substrate such that a bottom surface of the third insulating pattern and a top surface of the first insulating pattern face each other, a gate electrode between the bottom surface of the third insulating pattern and the top surface of the first insulating pattern, and including a first side extending between the bottom surface of the third insulating pattern and the top surface of the first insulating pattern, and a second insulating pattern that protrudes from the first side of the gate electrode by a second width in a second direction, the second direction being different from the first direction.

公开(公告)号：US11088163B2

公开(公告)日：2021-08-10

申请号：US16527506

申请日：2019-07-31

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kohji Kanamori ,  Yong Seok Kim ,  Kyung Hwan Lee ,  Jun Hee Lim ,  Jee Hoon Han

IPC: H01L27/11582 ,  H01L23/528 ,  H01L25/18 ,  H01L27/11573 ,  H01L25/00 ,  G11C16/08 ,  H01L29/78 ,  H01L29/10 ,  G11C16/04

Abstract: A semiconductor device includes a lower stack structure that includes a lower word line, an upper stack structure that is on the lower stack structure and includes an upper word line, a decoder that is adjacent to the lower stack structure and the upper stack structure, a signal interconnection that is connected to the decoder, a lower selector that is connected to the signal interconnection and further connected to the lower word line, and an upper selector that is connected to the signal interconnection, isolated from direct contact with the lower selector, and further connected to the upper word line.

公开(公告)号：US12207468B2

公开(公告)日：2025-01-21

申请号：US17681247

申请日：2022-02-25

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seung Yoon Kim ,  Sang Hun Chun ,  Jee Hoon Han

IPC: H01L21/00 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B41/40 ,  H10B43/10 ,  H10B43/27 ,  H10B43/35 ,  H10B43/40

Abstract: A semiconductor memory device includes a cell unit including a stack structure and a channel structure penetrating through the stack structure, the stack structure including at least one string selection gate and a plurality of cell gates, cell separation structures separating the cell unit in a first direction, and gate cutting structures defining regions within the cell unit between adjacent cell separation structures. The cell unit includes a first region defined between a first cell separation structure and a first gate cutting structure and a second region defined between the first gate cutting structure and a second gate cutting structure. A ratio of a region of the at least one string selection gate that is occupied by a conductive material in the second region is greater than a ratio of a region of at least one cell gate that is occupied by the conductive material in the second region.

公开(公告)号：US12046274B2

公开(公告)日：2024-07-23

申请号：US18460683

申请日：2023-09-04

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Kohji Kanamori ,  Sang Youn Jo ,  Jee Hoon Han

IPC: G11C7/10 ,  G11C11/4093 ,  H10B12/00

CPC classification number: G11C11/4093 ,  H10B12/50

Abstract: A nonvolatile memory device includes a first lower interlayer insulation layer and a second lower interlayer insulation layer that are sequentially stacked in a first direction; a lower metal layer disposed in the first lower interlayer insulation layer; and a plurality of lower bonding metals disposed in the first lower interlayer insulation layer and the second lower interlayer insulation layer and spaced apart from each other in a second direction that intersects the first direction. An uppermost surface in the first direction of the lower metal layer is lower than an uppermost surface in the first direction of the plurality of lower bonding metals, and the lower metal layer is placed between the plurality of lower bonding metals.

公开(公告)号：US11974433B2

公开(公告)日：2024-04-30

申请号：US17575947

申请日：2022-01-14

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Joo-Heon Kang ,  Tae Hun Kim ,  Jae Ryong Sim ,  Kwang Young Jung ,  Gi Yong Chung ,  Jee Hoon Han ,  Doo Hee Hwang

IPC: H10B43/27 ,  H10B43/35

CPC classification number: H10B43/27 ,  H10B43/35

Abstract: A semiconductor memory device includes a third insulating pattern and a first insulating pattern on a substrate, the third insulating pattern and the first insulating pattern being spaced apart from each other in a first direction that is perpendicular to the substrate such that a bottom surface of the third insulating pattern and a top surface of the first insulating pattern face each other, a gate electrode between the bottom surface of the third insulating pattern and the top surface of the first insulating pattern, and including a first side extending between the bottom surface of the third insulating pattern and the top surface of the first insulating pattern, and a second insulating pattern that protrudes from the first side of the gate electrode by a second width in a second direction, the second direction being different from the first direction.

公开(公告)号：US20240057336A1

公开(公告)日：2024-02-15

申请号：US18492504

申请日：2023-10-23

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Kohji Kanamori ,  Jee Hoon Han ,  Seo-Goo Kang ,  Hyo Joon Ryu

IPC: H10B43/27 ,  G11C8/14 ,  G11C7/18 ,  H10B41/10 ,  H10B41/27 ,  H10B41/40 ,  H10B43/10 ,  H10B43/40

CPC classification number: H10B43/27 ,  G11C8/14 ,  G11C7/18 ,  H10B41/10 ,  H10B41/27 ,  H10B41/40 ,  H10B43/10 ,  H10B43/40

Abstract: A semiconductor memory device includes; a lower stacked structure including lower metallic lines stacked in a first direction on a substrate, an upper stacked structure including a first upper metallic line and a second upper metallic line sequentially stacked on the lower stacked structure, a vertical structure penetrating the upper stacked structure and lower stacked structure and including a channel film, a connection pad disposed on the vertical structure, contacted with the channel film and doped with N-type impurities, a first cutting line cutting the lower metallic lines, the first upper metallic line and the second upper metallic line, a second cutting line spaced apart from the first cutting line in a second direction different from the first direction, and cutting the lower metallic lines, the first upper metallic line and the second upper metallic line, and sub-cutting lines cutting the first upper metallic line and the second upper metallic line between the first cutting line and the second cutting line. The channel film includes an undoped channel region and a doping channel region, and the doping channel region contacts the connection pad and overlaps a part of the second upper metallic line in the second direction.

公开(公告)号：US11729976B2

公开(公告)日：2023-08-15

申请号：US17370628

申请日：2021-07-08

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kohji Kanamori ,  Yong Seok Kim ,  Kyung Hwan Lee ,  Jun Hee Lim ,  Jee Hoon Han

IPC: H10B43/27 ,  H01L23/528 ,  H01L25/18 ,  H01L25/00 ,  G11C16/08 ,  H01L29/78 ,  H01L29/10 ,  G11C16/04 ,  H10B43/40

CPC classification number: H10B43/27 ,  G11C16/0483 ,  G11C16/08 ,  H01L23/528 ,  H01L25/18 ,  H01L25/50 ,  H01L29/1037 ,  H01L29/7827 ,  H10B43/40

Abstract: A semiconductor device includes a lower stack structure that includes a lower word line, an upper stack structure that is on the lower stack structure and includes an upper word line, a decoder that is adjacent to the lower stack structure and the upper stack structure, a signal interconnection that is connected to the decoder, a lower selector that is connected to the signal interconnection and further connected to the lower word line, and an upper selector that is connected to the signal interconnection, isolated from direct contact with the lower selector, and further connected to the upper word line.

公开(公告)号：US20250126801A1

公开(公告)日：2025-04-17

申请号：US18732848

申请日：2024-06-04

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Ju Seong Min ,  Hak Seon Kim ,  Jae-Bok Baek ,  Kang-Oh Yun ,  Taek Kyu Yoon ,  Dong Jin Lee ,  Jae Duk Lee ,  Se Jin Lim ,  Jee Hoon Han

IPC: H10B43/40 ,  H10B43/27

Abstract: The present disclosure relates to semiconductor memory devices. An example semiconductor memory device includes a cell region and a peripheral circuit region electrically connected with the cell region. The cell region includes a plurality of gate electrodes spaced apart from each other and stacked in a vertical direction, and a channel structure extending through the plurality of gate electrodes in the vertical direction. The peripheral circuit region includes a substrate, a first element isolation structure, a first gate structure on the first active region, a second element isolation structure, a second gate structure on the second active region, a third element isolation structure, and a third gate structure on the third active region. The third element isolation structure includes a first element isolation pattern and a second element isolation pattern. The first element isolation pattern and the second element isolation pattern include different materials from each other.