公开(公告)号：US10672436B2

公开(公告)日：2020-06-02

申请号：US16058709

申请日：2018-08-08

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Eun-Ji Kim ,  Jung-June Park ,  Jeong-Don Ihm ,  Byung-Hoon Jeong ,  Young-Don Choi

IPC: G11C7/10

Abstract: A memory device includes; a first memory chip including a first on-die Termination (ODT) circuit comprising a first ODT resistor, a second memory chip including a second ODT circuit comprising a second ODT resistor, at least one chip enable signal pin that receives at least one chip enable signal, wherein the at least one chip enable signal selectively enables at least one of the first memory chip and the second memory chip, and an ODT pin commonly connected to the first memory chip and the second memory chip that receives an ODT signal, wherein the ODT signal defines an enable period for at least one of the first ODT circuit and the second ODT circuit, and in response to the ODT signal and the at least one chip enable signal, one of the first ODT resistor and the second ODT resistor is enabled to terminate a signal received by at least one of the first memory chip and the second memory chip.

公开(公告)号：US20200091021A1

公开(公告)日：2020-03-19

申请号：US16357674

申请日：2019-03-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： Min-Jae Lee ,  Sang-Lok Kim ,  Byung-Hoon Jeong ,  Tae-Sung Lee ,  Jeong-Don Ihm ,  Jae-Yong Jeong ,  Young-Don Choi

IPC: H01L21/66 ,  H01L23/528

Abstract: A semiconductor device includes a semiconductor die, a defect detection structure and an input-output circuit. The semiconductor die includes a central region and a peripheral region surrounding the central region. The peripheral region includes a left-bottom corner region, a left-upper corner region, a right-upper corner region and a right-bottom corner region. The defect detection structure is formed in the peripheral region. The defect detection structure includes a first conduction loop in the left-bottom corner region, a second conduction loop in the right-bottom corner region, a third conduction loop in the left-bottom corner region and the left-upper corner region and a fourth conduction loop in the right-bottom corner region and the right-upper corner region. The input-output circuit is electrically connected to end nodes of the first conduction loop, the second conduction loop, the third conduction loop and the fourth conduction loop.

公开(公告)号：US10559373B2

公开(公告)日：2020-02-11

申请号：US16458933

申请日：2019-07-01

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Eun-Ji Kim ,  Jung-June Park ,  Jeong-Don Ihm ,  Byung-Hoon Jeong ,  Young-Don Choi

IPC: G11C7/10 ,  G11C29/02 ,  G11C5/06 ,  G11C16/26 ,  G11C16/10 ,  G11C16/06

Abstract: A nonvolatile memory (NVM) device includes a data pin, a control pin, an on-die termination (ODT) pin, and a plurality of NVM memory chips commonly connected to the data pin and the control pin. A first NVM chip among the NVM chips includes an ODT circuit. The first NVM chip determines one of an ODT write mode and an ODT read mode based on a control signal received through the control pin and an ODT signal received through the ODT pin, uses the ODT circuit to perform an ODT on the data pin during the ODT write mode, and uses the ODT circuit to perform the ODT on the control pin during the ODT read mode.

公开(公告)号：US10291275B2

公开(公告)日：2019-05-14

申请号：US15397012

申请日：2017-01-03

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seon-Kyoo Lee ,  Byung-Hoon Jeong ,  Jeong-Don Ihm ,  Young-Don Choi

IPC: H03F1/32 ,  H03F1/34 ,  H04B1/24 ,  H04L25/03 ,  H04L12/863 ,  H04L25/02 ,  H04L12/861

Abstract: A reception interface circuit includes a termination circuit, a buffer and an interface controller. The termination circuit is configured to change a termination mode in response to a termination control signal. The buffer is configured to change a reception characteristic in response to a buffer control signal. The interface controller is configured to generate the termination control signal and the buffer control signal such that the reception characteristic of the buffer is changed in association with the change in the termination mode. The reception interface circuit may support various communication standards by changing the reception characteristic of the buffer in association with the termination mode. Using the reception interface circuit, communication efficiency of transceiver systems such as a memory system and/or compatibility between a transmitter device and a receiver device may be improved.

公开(公告)号：US12073898B2

公开(公告)日：2024-08-27

申请号：US18361132

申请日：2023-07-28

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Eun-Ji Kim ,  Jung-June Park ,  Jeong-Don Ihm ,  Byung-Hoon Jeong ,  Young-Don Choi

IPC: G11C5/06 ,  G11C7/10 ,  G11C16/06 ,  G11C16/10 ,  G11C16/26 ,  G11C29/02

CPC classification number: G11C29/025 ,  G11C5/063 ,  G11C7/1048 ,  G11C7/1057 ,  G11C7/1084 ,  G11C16/06 ,  G11C16/102 ,  G11C16/26 ,  G11C29/022 ,  G11C29/028

Abstract: A nonvolatile memory (NVM) device includes a data pin, a control pin, an on-die termination (ODT) pin, and a plurality of NVM memory chips commonly connected to the data pin and the control pin. A first NVM chip among the NVM chips includes an ODT circuit. The first NVM chip determines one of an ODT write mode and an ODT read mode based on a control signal received through the control pin and an ODT signal received through the ODT pin, uses the ODT circuit to perform an ODT on the data pin during the ODT write mode, and uses the ODT circuit to perform the ODT on the control pin during the ODT read mode.

公开(公告)号：US11342038B2

公开(公告)日：2022-05-24

申请号：US17161995

申请日：2021-01-29

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Eun-Ji Kim ,  Jung-June Park ,  Jeong-Don Ihm ,  Byung-Hoon Jeong ,  Young-Don Choi

IPC: G11C7/10 ,  G11C16/26 ,  G11C16/06 ,  G11C29/02 ,  G11C5/06 ,  G11C16/10

Abstract: A nonvolatile memory (NVM) device includes a data pin, a control pin, an on-die termination (ODT) pin, and a plurality of NVM memory chips commonly connected to the data pin and the control pin. A first NVM chip among the NVM chips includes an ODT circuit. The first NVM chip determines one of an ODT write mode and an ODT read mode based on a control signal received through the control pin and an ODT signal received through the ODT pin, uses the ODT circuit to perform an ODT on the data pin during the ODT write mode, and uses the ODT circuit to perform the ODT on the control pin during the ODT read mode.

公开(公告)号：US10438635B2

公开(公告)日：2019-10-08

申请号：US16113500

申请日：2018-08-27

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seon-Kyoo Lee ,  Dae-Hoon Na ,  Jeong-Don Ihm ,  Byung-Hoon Jeong ,  Young-Don Choi

IPC: G11C7/10 ,  G11C7/06 ,  H01L25/065 ,  G11C7/22 ,  H01L23/00

Abstract: An apparatus includes data transmitter having first through N-th data drivers configured to provide first through N-th data signals, respectively, and a strobe driver configured to provide a strobe signal, and a data receiver having a strobe buffer configured to generate a control signal based on the strobe signal, and first through N-th sense amplifiers configured to sense N-bit data based on the control signal, a reference signal and the first through N-th data signals. The bus includes a strobe TSV configured to connect the strobe driver with the strobe buffer, and first through N-th data TSVs configured to connect the first through N-th data drivers with the first through N-th sense amplifiers, respectively. A reference signal supplier controls the reference signal such that a discharge speed of the reference signal is slower than a discharge speed of each of the first through N-th data signals during data transmission.

公开(公告)号：US20190279733A1

公开(公告)日：2019-09-12

申请号：US16426391

申请日：2019-05-30

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Eun-Ji Kim ,  Jung-June Park ,  Jeong-Don Ihm ,  Byung-Hoon Jeong ,  Young-Don Choi

IPC: G11C29/02 ,  G11C5/06 ,  G11C7/10 ,  G11C16/06 ,  G11C16/26 ,  G11C16/10

Abstract: A nonvolatile memory (NVM) device includes a data pin, a control pin, an on-die termination (ODT) pin, and a plurality of NVM memory chips commonly connected to the data pin and the control pin. A first NVM chip among the NVM chips includes an ODT circuit. The first NVM chip determines one of an ODT write mode and an ODT read mode based on a control signal received through the control pin and an ODT signal received through the ODT pin, uses the ODT circuit to perform an ODT on the data pin during the ODT write mode, and uses the ODT circuit to perform the ODT on the control pin during the ODT read mode.

公开(公告)号：US09904310B2

公开(公告)日：2018-02-27

申请号：US15224927

申请日：2016-08-01

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jeong-Don Ihm ,  Siddharth Katare

IPC: G05F1/44 ,  G05F3/26

CPC classification number: G05F3/262

Abstract: A regulator circuit includes a power transistor, a current mirror, a first NMOS transistor, a second NMOS transistor and a current source. The power transistor has a source connected to an external power supply voltage supply, a gate connected to a first node having a first voltage and a drain connected to a second node outputting an internal power supply voltage. A current mirror provides a first current to a third node having a second voltage and provides a first node with a second current. A first NMOS transistor has a drain connected to a first node, a gate receiving a first reference voltage and a source connected to a fourth node. A second NMOS transistor has a drain connected to a third node, a gate connected to a second node and a source connected to the fourth node.

公开(公告)号：US11600539B2

公开(公告)日：2023-03-07

申请号：US17356152

申请日：2021-06-23

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Min-Jae Lee ,  Sang-Lok Kim ,  Byung-Hoon Jeong ,  Tae-Sung Lee ,  Jeong-Don Ihm ,  Jae-Yong Jeong ,  Young-Don Choi

IPC: G01R31/64 ,  H01L21/66 ,  H01L23/528 ,  G01R31/3187

Abstract: A semiconductor device includes a semiconductor die, a defect detection structure and an input-output circuit. The semiconductor die includes a central region and a peripheral region surrounding the central region. The peripheral region includes a left-bottom corner region, a left-upper corner region, a right-upper corner region and a right-bottom corner region. The defect detection structure is formed in the peripheral region. The defect detection structure includes a first conduction loop in the left-bottom corner region, a second conduction loop in the right-bottom corner region, a third conduction loop in the left-bottom corner region and the left-upper corner region and a fourth conduction loop in the right-bottom corner region and the right-upper corner region. The input-output circuit is electrically connected to end nodes of the first conduction loop, the second conduction loop, the third conduction loop and the fourth conduction loop.