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    MEMORY PACKAGE AND STORAGE DEVICE INCLUDING THE SAME
    11.
    发明申请
    MEMORY PACKAGE AND STORAGE DEVICE INCLUDING THE SAME 有权

    公开(公告)号：US20220157353A1

    公开(公告)日：2022-05-19

    申请号：US17361780

    申请日：2021-06-29

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Joohwan KIM ,  Jindo BYUN ,  Younghoon SON ,  Youngdon CHOI ,  Junghwan CHOI

    IPC: G11C7/10 ,  G06F3/06 ,  G11C7/22

    Abstract: A memory package includes a package substrate including a redistribution layer and bonding pads connected to the redistribution layer, the redistribution layer including a plurality of signal paths; a buffer chip mounted on the package substrate and including a plurality of chip pads corresponding to a plurality of memory channels; and a plurality of memory chips stacked on the package substrate and divided into a plurality of groups corresponding to the plurality of memory channels, wherein memory chips of a first group, among the plurality of memory chips, are connected to first chip pads of the plurality of chip pads through first wires, and wherein memory chips of a second group, among the plurality of memory chips, are connected to second chip pads of the plurality of chip pads through second wires and at least a portion of the plurality of signal paths.

    MEMORY DEVICE, OPERATING METHOD OF THE SAME, AND MEMORY SYSTEM
    12.
    发明申请
    MEMORY DEVICE, OPERATING METHOD OF THE SAME, AND MEMORY SYSTEM 有权

    公开(公告)号：US20220068331A1

    公开(公告)日：2022-03-03

    申请号：US17230403

    申请日：2021-04-14

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Mingyu LEE ,  Jaewoo PARK ,  Younghoon SON ,  Youngdon CHOI ,  Hyungmin JIN ,  Junghwan CHOI

    IPC: G11C7/22 ,  G11C7/06 ,  G06F13/16

    Abstract: A method of operating a memory device including receiving a multilevel signal having M levels transmitted by an external controller through a clock receiving pin, where M is a natural number greater than 2, and decoding the multilevel signal to restore at least one of Data Bus Inversion (DBI) data, Data Mask (DM) data, Cyclic Redundancy Check (CRC) data, or Error Correction Code (ECC) data may be provided. The multilevel signal is a clock signal transmitted by the external controller, and is a signal swinging based on an intermediate reference signal that is an intermediate value between a minimum level and a maximum level among the M levels.

    METHOD AND APPARATUS FOR REGENERATION AND PREDICTION OF TREE MAP
    13.
    发明申请
    METHOD AND APPARATUS FOR REGENERATION AND PREDICTION OF TREE MAP 有权

    公开(公告)号：US20210183142A1

    公开(公告)日：2021-06-17

    申请号：US17123811

    申请日：2020-12-16

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Soonyoung LEE ,  Yoonsung PARK ,  Junghwan CHOI

    IPC: G06T17/05 ,  G06T7/10 ,  G06T7/90

    Abstract: A pre-5th-Generation (5G) or 5G communication system for supporting higher data rates Beyond 4th-Generation (4G) communication system such as long term evolution (LTE) is provided. The method for operating a server includes receiving a first image including at least one tree, determining whether to generate a tree map based on the first image, based on a difference between first tree region data of the first image and second tree region data of a second image which is prestored, and generating the tree map according to determining.

    MEMORY DEVICE SUPPORTING A HIGH-EFFICIENT INPUT/OUTPUT INTERFACE AND A MEMORY SYSTEM INCLUDING THE MEMORY DEVICE
    14.
    发明申请
    MEMORY DEVICE SUPPORTING A HIGH-EFFICIENT INPUT/OUTPUT INTERFACE AND A MEMORY SYSTEM INCLUDING THE MEMORY DEVICE 有权

    公开(公告)号：US20240370386A1

    公开(公告)日：2024-11-07

    申请号：US18772354

    申请日：2024-07-15

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Hyungmin JIN ,  Jindo BYUN ,  Younghoon SON ,  Youngdon CHOI ,  Junghwan CHOI

    IPC: G06F13/16 ,  H04L25/49

    Abstract: A memory system including: a memory controller to transmit a command, an address, or data to a first channel based on a data input/output signal having one of N (N is a natural number of three or more) different voltage levels during a first time interval, the memory controller transmitting the command, the address, or the data not transmitted during the first time interval to the first channel based on the data input/output signal having one of two different voltage levels during a second time interval; and a memory device to sample the data input/output signal received via the first channel during the first time interval in a pulse amplitude modulation (PAM)-N mode, the memory device sampling the data input/output signal received via the first channel during the second time interval in a non return to zero (NRZ) mode.

    SEMICONDUCTOR DEVICE
    15.
    发明公开
    SEMICONDUCTOR DEVICE 审中-公开

    公开(公告)号：US20240187002A1

    公开(公告)日：2024-06-06

    申请号：US18350606

    申请日：2023-07-11

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Jinwook LEE ,  Joohwan KIM ,  Junyoung PARK ,  Jindo BYUN ,  Eunseok SHIN ,  Junghwan CHOI

    IPC: H03L7/081 ,  G11C7/22 ,  H03K5/135

    CPC classification number: H03L7/0812 ,  G11C7/222 ,  H03K5/135

    Abstract: A semiconductor device includes a phase splitter configured to output a plurality of clock signals having different phases by using a plurality of external clock signals having different phases, a plurality of code generators configured to receive a pair of selection clock signals determined from the plurality of clock signals and to output a phase code corresponding to a phase difference error between the pair of selection clock signals, and a delay circuit configured to at least partly simultaneously adjust at least two of a rising edge and a falling edge of each of the plurality of external clock signals with reference to the phase code during a lock time.

    TRANSMITTER FOR ULTRA-HIGH SPEED AND STORAGE DEVICE INCLUDING THE SAME
    16.
    发明公开
    TRANSMITTER FOR ULTRA-HIGH SPEED AND STORAGE DEVICE INCLUDING THE SAME 审中-公开

    公开(公告)号：US20240168091A1

    公开(公告)日：2024-05-23

    申请号：US18325162

    申请日：2023-05-30

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Ikjin JO ,  Jaewoo PARK ,  Jueon KIM ,  Myoungbo KWAK ,  Junghwan CHOI

    IPC: G01R31/317 ,  G01R31/319

    CPC classification number: G01R31/31727 ,  G01R31/31726 ,  G01R31/31926

    Abstract: A transmitter includes a data generator, a serializer, a transmission driver and a feedback circuit. The data generator generates a retimed data signal and retimed test data by adjusting a delay amount of each of an input data signal and a test data based on adjusted clock signals. The serializer generates a serial data signal by serializing the retimed data signal based on multi-phase clock signals. The transmission driver generates an output data signal based on the serial data signal and transmits the output data signal through a channel. The feedback circuit detects the setup margin and the hold margin of the retimed test data through a separate path different from a path of the retimed data signal and generates the adjusted clock signals by adjusting delay amounts of the multi-phase clock signals based on the detected setup margin and hold margin of the retimed test data.

    MEMORY DEVICE AND OPERATING METHOD OF A MEMORY DEVICE
    17.
    发明公开
    MEMORY DEVICE AND OPERATING METHOD OF A MEMORY DEVICE 审中-公开

    公开(公告)号：US20230353132A1

    公开(公告)日：2023-11-02

    申请号：US18219254

    申请日：2023-07-07

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Mingyu LEE ,  Youngchul CHO ,  Seungjin PARK ,  Youngdon CHOI ,  Junghwan CHOI

    IPC: H03K5/06 ,  H03K5/05 ,  H03K5/15

    CPC classification number: H03K5/06 ,  H03K5/05 ,  H03K5/1506 ,  H03K5/1508

    Abstract: A clock signal delay path unit includes a first delay cell including a first root signal line for delaying and transmitting a clock signal, a first repeater to transmit the clock signal transmitted through the first root signal line without signal attenuation, and a second root signal line for delaying and transmitting the clock signal output from the first repeater, a second delay cell including a first inverting circuit configured to invert the clock signal provided from the first delay cell to generate an inverted clock signal, and a third delay cell including a first branch signal line for delaying and transmitting the inverted clock signal provided from the second delay cell, a second repeater to transmit the inverted clock signal transmitted through the first branch signal line, and a second branch signal line for delaying and transmitting the inverted clock signal output from the second repeater.

    TRANSMITTER CIRCUIT INCLUDING SELECTION CIRCUIT, AND METHOD OF OPERATING THE SELECTION CIRCUIT
    19.
    发明申请
    TRANSMITTER CIRCUIT INCLUDING SELECTION CIRCUIT, AND METHOD OF OPERATING THE SELECTION CIRCUIT 有权

    公开(公告)号：US20220385287A1

    公开(公告)日：2022-12-01

    申请号：US17751148

    申请日：2022-05-23

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Junyoung PARK ,  Joohwan KIM ,  Jindo BYUN ,  Eunseok SHIN ,  Hyunyoon CHO ,  Youngdon CHOI ,  Junghwan CHOI

    IPC: H03K17/693 ,  H03K19/20

    Abstract: A transmitter circuit includes a clock generator configured to generate a plurality of clock signals having different phases, and a plurality of selection circuits configured to receive a plurality of parallel data signals and output a serial data signal on an output node based on the plurality of clock signals and the received plurality of parallel data signals. Each of the plurality of selection circuits includes a data multiplexer configured to generate a plurality of data selection signals based on the received one of the plurality of parallel data signals and the plurality of clock signals; a control signal generator configured to generate first and second control signals based on the plurality of data selection signals; and an output driver connected to the output node, and configured to precharge the output node based on the first control signal or discharge the output node based on the second control signal.

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