公开(公告)号：US20230411458A1

公开(公告)日：2023-12-21

申请号：US18239660

申请日：2023-08-29

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Ilgyou Shin ,  Minyi Kim ,  Myung Gil Kang ,  Jinbum Kim ,  Seung Hun Lee ,  Keun Hwi Cho

IPC: H01L29/15 ,  H01L29/78 ,  H01L29/417 ,  H01L29/10

CPC classification number: H01L29/158 ,  H01L29/1033 ,  H01L29/41791 ,  H01L29/785

Abstract: A semiconductor device includes; a substrate including a first region and a second region, a first active pattern extending upward from the first region, a first superlattice pattern on the first active pattern, a first active fin centrally disposed on the first active pattern, a first gate electrode disposed on the first active fin, and first source/drain patterns disposed on opposing sides of the first active fin and on the first active pattern. The first superlattice pattern includes at least one first semiconductor layer and at least one first blocker-containing layer, and the first blocker-containing layer includes at least one of oxygen, carbon, fluorine and nitrogen.

公开(公告)号：US11769813B2

公开(公告)日：2023-09-26

申请号：US18046518

申请日：2022-10-14

Applicant: Samsung Electronics Co., Ltd.

Inventor： Myung Gil Kang ,  Dong Won Kim ,  Woo Seok Park ,  Keun Hwi Cho ,  Sung Gi Hur

IPC: H01L29/423 ,  H01L27/092 ,  H01L29/06 ,  H01L29/786

CPC classification number: H01L29/42392 ,  H01L27/092 ,  H01L29/0665 ,  H01L29/4236 ,  H01L29/78696

Abstract: Semiconductor devices include a first active pattern including a first lower pattern extending in a first direction and a first sheet pattern spaced apart from the first lower pattern; and a first gate electrode on the first lower pattern, the first gate electrode extending in a second direction different from the first direction and surrounding the first sheet pattern, wherein the first lower pattern includes a first sidewall and a second sidewall opposite to each other, each of the first sidewall of the first lower pattern and the second sidewall of the first lower pattern extends in the first direction, the first gate electrode overlaps the first sidewall of the first lower pattern in the second direction by a first depth, the first gate electrode overlaps the second sidewall of the first lower pattern in the second direction by a second depth, and the first depth is different from the second depth.

公开(公告)号：US11563004B2

公开(公告)日：2023-01-24

申请号：US16789588

申请日：2020-02-13

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Myoung-Sun Lee ,  Keun Hwi Cho

IPC: H01L27/092 ,  H01L27/02 ,  H01L21/8238 ,  H01L29/08 ,  H01L29/78 ,  H01L29/165 ,  H01L21/02 ,  H01L29/417

Abstract: There is provided a semiconductor device having enhanced operation performance by utilizing a cut region where a gate cut is implemented. There is provided a semiconductor device comprising a first active pattern, a second active pattern, a third active pattern, and a fourth active pattern, all of which extend in parallel in a first direction, and are arranged along a second direction intersecting the first direction; a first gate electrode extended in the second direction on the first to fourth active patterns a first cut region extended in the first direction between the first active pattern and the second active pattern to cut the first gate electrode and a second cut region extended in the first direction between the third active pattern and the fourth active pattern to cut the first gate electrode, wherein one or more first dimensional features related to the first cut region is different from one or more second dimensional features related to the second cut region.

公开(公告)号：US11482606B2

公开(公告)日：2022-10-25

申请号：US17209290

申请日：2021-03-23

Applicant: Samsung Electronics Co., Ltd.

Inventor： Myung Gil Kang ,  Dong Won Kim ,  Woo Seok Park ,  Keun Hwi Cho ,  Sung Gi Hur

IPC: H01L29/423 ,  H01L27/092 ,  H01L29/786 ,  H01L29/06

Abstract: Semiconductor devices include a first active pattern including a first lower pattern extending in a first direction and a first sheet pattern spaced apart from the first lower pattern; and a first gate electrode on the first lower pattern, the first gate electrode extending in a second direction different from the first direction and surrounding the first sheet pattern, wherein the first lower pattern includes a first sidewall and a second sidewall opposite to each other, each of the first sidewall of the first lower pattern and the second sidewall of the first lower pattern extends in the first direction, the first gate electrode overlaps the first sidewall of the first lower pattern in the second direction by a first depth, the first gate electrode overlaps the second sidewall of the first lower pattern in the second direction by a second depth, and the first depth is different from the second depth.

公开(公告)号：US11417731B2

公开(公告)日：2022-08-16

申请号：US17128153

申请日：2020-12-20

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jinbum Kim ,  Dahye Kim ,  Seokhoon Kim ,  Jaemun Kim ,  Ilgyou Shin ,  Haejun Yu ,  Kyungin Choi ,  Kihyun Hwang ,  Sangmoon Lee ,  Seung Hun Lee ,  Keun Hwi Cho

IPC: H01L29/08 ,  H01L27/092 ,  H01L29/165 ,  H01L29/423 ,  H01L29/66 ,  H01L29/78 ,  H01L29/786 ,  H01L29/161 ,  H01L29/06 ,  H01L21/8238

Abstract: A semiconductor device includes an active pattern on a substrate, a pair of source/drain patterns on the active pattern, a channel pattern between the pair of source/drain patterns, the channel pattern including semiconductor patterns stacked to be spaced apart from each other, and a gate electrode crossing the channel pattern and extending in a first direction. One of the pair of source/drain patterns includes a first semiconductor layer and a second semiconductor layer thereon. The first semiconductor layer is in contact with a first semiconductor pattern, which is one of the stacked semiconductor patterns. The largest widths of the first semiconductor pattern, the first semiconductor layer, and the second semiconductor layer in the first direction are a first width, a second width, a third width, respectively, and the second width is larger than the first width and smaller than the third width.

公开(公告)号：US20160087026A1

公开(公告)日：2016-03-24

申请号：US14718685

申请日：2015-05-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： Myung Gil Kang ,  Dongwon Kim ,  Ilryong Kim ,  Changwoo Oh ,  Keun Hwi Cho ,  Toshinori Fukai

IPC: H01L49/02 ,  H01L27/06

CPC classification number: H01L28/20 ,  H01L27/0629

Abstract: Embodiments of the inventive concepts provide a resistor and a semiconductor device including the same. The resistor includes a substrate, a device isolation layer in the substrate which defines active regions arranged in a first direction a resistance layer including resistance patterns that vertically protrude from the active regions and are connected to each other in the first direction, and contact electrodes on the resistance layer.

Abstract translation: 本发明构思的实施例提供一种电阻器和包括该电阻器的半导体器件。 电阻器包括衬底，衬底中的器件隔离层，其限定在第一方向上布置的有源区，包括从有源区垂直突出并在第一方向上彼此连接的电阻图案的电阻层，以及接触电极 电阻层。

公开(公告)号：US20250120149A1

公开(公告)日：2025-04-10

申请号：US18949790

申请日：2024-11-15

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Ilgyou Shin ,  Minyi Kim ,  Myung Gil Kang ,  Jinbum Kim ,  Seung Hun Lee ,  Keun Hwi Cho

IPC: H10D62/815 ,  H10D30/62 ,  H10D62/17

Abstract: A semiconductor device includes; a substrate including a first region and a second region, a first active pattern extending upward from the first region, a first superlattice pattern on the first active pattern, a first active fin centrally disposed on the first active pattern, a first gate electrode disposed on the first active fin, and first source/drain patterns disposed on opposing sides of the first active fin and on the first active pattern. The first superlattice pattern includes at least one first semiconductor layer and at least one first blocker-containing layer, and the first blocker-containing layer includes at least one of oxygen, carbon, fluorine and nitrogen.

公开(公告)号：US12166081B2

公开(公告)日：2024-12-10

申请号：US18239660

申请日：2023-08-29

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Ilgyou Shin ,  Minyi Kim ,  Myung Gil Kang ,  Jinbum Kim ,  Seung Hun Lee ,  Keun Hwi Cho

IPC: H01L29/15 ,  H01L29/10 ,  H01L29/417 ,  H01L29/78

Abstract: A semiconductor device includes; a substrate including a first region and a second region, a first active pattern extending upward from the first region, a first superlattice pattern on the first active pattern, a first active fin centrally disposed on the first active pattern, a first gate electrode disposed on the first active fin, and first source/drain patterns disposed on opposing sides of the first active fin and on the first active pattern. The first superlattice pattern includes at least one first semiconductor layer and at least one first blocker-containing layer, and the first blocker-containing layer includes at least one of oxygen, carbon, fluorine and nitrogen.

公开(公告)号：US12009404B2

公开(公告)日：2024-06-11

申请号：US17686504

申请日：2022-03-04

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seungseok Ha ,  Gukil An ,  Keun Hwi Cho ,  Sungmin Kim

IPC: H01L29/51 ,  H01L29/423 ,  H01L29/49 ,  H01L29/786

CPC classification number: H01L29/516 ,  H01L29/42364 ,  H01L29/42392 ,  H01L29/4966 ,  H01L29/78696

Abstract: Semiconductor devices and methods of forming the same are provided. The semiconductor devices may include a substrate, a pair of semiconductor patterns adjacent to each other on the substrate, a gate electrode on the pair of semiconductor patterns, a source/drain pattern connected to the pair of semiconductor patterns, and a ferroelectric pattern on surfaces of the pair of semiconductor patterns. The surfaces of the pair of semiconductor patterns may face each other, and the ferroelectric pattern may define a first space between the pair of semiconductor patterns. The gate electrode may include a work function metal pattern that is in the first space.

公开(公告)号：US20240145476A1

公开(公告)日：2024-05-02

申请号：US18408098

申请日：2024-01-09

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Myoung-Sun LEE ,  Keun Hwi Cho

IPC: H01L27/092 ,  H01L27/02

CPC classification number: H01L27/0924 ,  H01L27/0207 ,  H01L21/823814

Abstract: There is provided a semiconductor device having enhanced operation performance by utilizing a cut region where a gate cut is implemented. There is provided a semiconductor device comprising a first active pattern, a second active pattern, a third active pattern, and a fourth active pattern, all of which extend in parallel in a first direction, and are arranged along a second direction intersecting the first direction; a first gate electrode extended in the second direction on the first to fourth active patterns a first cut region extended in the first direction between the first active pattern and the second active pattern to cut the first gate electrode and a second cut region extended in the first direction between the third active pattern and the fourth active pattern to cut the first gate electrode, wherein one or more first dimensional features related to the first cut region is different from one or more second dimensional features related to the second cut region.