公开(公告)号：US20200347494A1

公开(公告)日：2020-11-05

申请号：US16861614

申请日：2020-04-29

Applicant: Samsung Electronics Co., Ltd. ,  Research & business foundation sungkyunkwan university

Inventor： Kyung-Eun BYUN ,  Hyoungsub KIM ,  Taejin PARK ,  Hyeonjin SHIN ,  Hoijoon KIM ,  Wonsik AHN ,  Mirine LEEM

IPC: C23C16/30 ,  B22F7/00 ,  C23C16/46

Abstract: Provided are a metal chalcogenide thin film and a method and device for manufacturing the same. The metal chalcogenide thin film includes a transition metal element and a chalcogen element, and at least one of the transition metal element and the chalcogen element having a composition gradient along the surface of the metal chalcogenide thin film, the composition gradient being an in-plane composition gradient. The metal chalcogenide thin film may be prepared by using a manufacturing method including providing a transition metal precursor and a chalcogen precursor on a substrate by using a confined reaction space in such a manner that at least one of the transition metal precursor and the chalcogen precursor forms a concentration gradient according to a position on the surface of the substrate; and heat-treating the substrate.

公开(公告)号：US20250142874A1

公开(公告)日：2025-05-01

申请号：US18660936

申请日：2024-05-10

Applicant: Samsung Electronics Co., Ltd.

Inventor： Changhyun KIM ,  Kyung-Eun BYUN ,  Minsu SEOL ,  Junyoung KWON ,  Huije RYU ,  Eunkyu LEE ,  Yeonchoo CHO

IPC: H01L29/78 ,  H01L27/092 ,  H01L29/10 ,  H01L29/66

Abstract: Provided is a semiconductor device including a substrate, a first vertical channel, a spacer, and a second vertical channel. The first vertical channel may have a sheet shape extending in a direction perpendicular to a surface of the substrate. The spacer may be provided at an end of the first vertical channel in an extension direction. The second vertical channel may be aligned with the first vertical channel on the spacer and have a sheet shape extending in a vertical direction.

公开(公告)号：US20250126846A1

公开(公告)日：2025-04-17

申请号：US18613829

申请日：2024-03-22

Applicant: Samsung Electronics Co., Ltd.

Inventor： Junyoung KWON ,  Changhyun KIM ,  Kyung-Eun BYUN ,  Minsu SEOL

IPC: H01L29/786 ,  H01L29/41 ,  H01L29/417 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775

Abstract: A semiconductor device includes a first channel layer and a second channel layer spaced from each other in a first direction and each include a two-dimensional (2D) semiconductor material, a first source electrode between the first channel layer and the second channel layer to be simultaneously in contact with the first channel layer and the second channel layer, a first drain electrode between the first channel layer and the second channel layer to be spaced apart from the first source electrode in a second direction perpendicular to the first direction and simultaneously in contact with the first channel layer and the second channel layer, a first gate electrode arranged in a first internal space surrounded by the first source electrode, the first drain electrode, the first channel layer, and the second channel layer, and a first gate insulating layer surrounding the first gate electrode in the first internal space.

公开(公告)号：US20240297221A1

公开(公告)日：2024-09-05

申请号：US18405389

申请日：2024-01-05

Applicant: Samsung Electronics Co., Ltd. ,  University-Industry Cooperation Group Of Kyung Hee University

Inventor： Changseok LEE ,  Seunghyun LEE ,  Minsu SEOL ,  Dohee KIM ,  Junseong BAE ,  Hyeyoon RYU ,  Sangwon KIM ,  Kyung-Eun BYUN

IPC: H01L29/16 ,  H01L29/167 ,  H01L29/417 ,  H01L29/778

CPC classification number: H01L29/1606 ,  H01L29/167 ,  H01L29/41725 ,  H01L29/778

Abstract: A transistor structure may include a semiconductor structure may include a substrate; a source electrode and a drain electrode spaced apart from each other on the substrate; a channel layer connected to the source electrode and the drain electrode; a gate insulating layer on the channel layer; and a gate electrode on the gate insulating layer. The channel layer may include a two-dimensional semiconductor material. The source electrode and the drain electrode each may include a graphene layer and a metal layer. The graphene layer may be formed by as-growing on the substrate. The graphene layer and the metal layer may be side by side in a vertical direction with respect to a surface of the substrate.

公开(公告)号：US20240222432A1

公开(公告)日：2024-07-04

申请号：US18401855

申请日：2024-01-02

Applicant: Samsung Electronics Co., Ltd.

Inventor： Joungeun YOO ,  Duseop YOON ,  Kyung-Eun BYUN ,  Minsu SEOL

IPC: H01L29/06 ,  H01L29/417 ,  H01L29/786

CPC classification number: H01L29/0673 ,  H01L29/41725 ,  H01L29/78696

Abstract: A semiconductor device may include a two-dimensional (2D) material layer having semiconductor characteristics, and a source electrode, a drain electrode, and a gate electrode spaced apart from one another on the 2D material layer. At least one of the source electrode and the drain electrode may be in contact with the 2D material layer and may include an alloy layer that may be amorphous.

公开(公告)号：US20240151522A1

公开(公告)日：2024-05-09

申请号：US18412823

申请日：2024-01-15

Applicant: Samsung Electronics Co., Ltd.

Inventor： Eunkyu LEE ,  Yeonchoo CHO ,  Sangwon KIM ,  Kyung-Eun BYUN ,  Hyunjae SONG ,  Hyeonjin SHIN

IPC: G01B15/02 ,  G01N23/2208 ,  G01N23/2273 ,  H01L21/285 ,  H01L21/66 ,  H01L29/45

CPC classification number: G01B15/02 ,  G01N23/2208 ,  G01N23/2273 ,  H01L21/28512 ,  H01L22/12 ,  H01L29/45 ,  G01N2223/085 ,  G01N2223/61

Abstract: A method of calculating a thickness of a graphene layer and a method of measuring a content of silicon carbide, by using X-ray photoelectron spectroscopy (XPS), are provided. The method of calculating the thickness of the graphene layer, which is directly grown on a silicon substrate, includes measuring the thickness of the graphene layer directly grown on the silicon substrate, by using a ratio between a signal intensity of a photoelectron beam emitted from the graphene layer and a signal intensity of a photoelectron beam emitted from the silicon substrate.

公开(公告)号：US20230157022A1

公开(公告)日：2023-05-18

申请号：US17986371

申请日：2022-11-14

Applicant: Samsung Electronics Co., Ltd.

Inventor： Keunwook SHIN ,  Changhyun KIM ,  Sehun PARK ,  Hyunwoo KIM ,  Kyung-Eun BYUN ,  Dongjin YUN ,  Changseok LEE

IPC: H01L27/11582 ,  G06N3/063

CPC classification number: H01L27/11582 ,  G06N3/0635

Abstract: A vertical nonvolatile memory device may include a channel layer extending in a first direction; a plurality of gate electrodes and a plurality of spacers each extending in a second direction crossing the first direction, the plurality of gate electrodes and the plurality of spacers being alternately arranged with each other in the first direction; and a gate insulating layer extending in the first direction between the channel layer and the plurality of gate electrodes. Each of the plurality of gate electrodes may include a metal-doped graphene.

公开(公告)号：US20230096121A1

公开(公告)日：2023-03-30

申请号：US17882169

申请日：2022-08-05

Applicant: Samsung Electronics Co., Ltd.

Inventor： Alum JUNG ,  Kyung-Eun BYUN ,  Keunwook SHIN

IPC: H01L29/06 ,  H01L21/02

Abstract: A stacked structure may include a first material layer, a two-dimensional material layer on the first material layer, and a second material layer on the two-dimensional material layer. The two-dimensional material layer may include a plurality of holes that each expose a portion of the first material layer. The second material layer may be coupled to the first material layer through the plurality of holes.

公开(公告)号：US20230081646A1

公开(公告)日：2023-03-16

申请号：US17902111

申请日：2022-09-02

Applicant: Samsung Electronics Co., Ltd.

Inventor： Changhyun KIM ,  Unki KIM ,  Alum JUNG ,  Kyung-Eun BYUN

IPC: H01L29/08 ,  H01L29/06 ,  H01L29/161 ,  H01L29/423 ,  H01L29/775 ,  H01L21/02 ,  H01L21/306 ,  H01L29/66

Abstract: A multi bridge channel field effect transistor includes a substrate, a first source/drain pattern on the substrate, a second source/drain pattern apart from the first source/drain pattern in a first direction on the substrate, a first channel layer and a second channel layer between the first source/drain pattern and the second source/drain pattern, a first graphene barrier between the first channel layer and the first source/drain pattern, a gate insulating layer surrounding the first channel layer, and a gate electrode surrounding the first channel layer with the gate insulating layer therebetween.

公开(公告)号：US20230024913A1

公开(公告)日：2023-01-26

申请号：US17949418

申请日：2022-09-21

Applicant: Samsung Electronics Co., Ltd. ,  RESEARCH & BUSINESS FOUNDATION SUNGKYUNKWAN UNIVERSITY

Inventor： Kyung-Eun BYUN ,  Hyoungsub KIM ,  Taejin PARK ,  Hoijoon KIM ,  Hyeonjin SHIN ,  Wonsik AHN ,  Mirine LEEM ,  Yeonchoo CHO

IPC: H01L21/02

Abstract: A method of forming a transition metal dichalcogenide thin film on a substrate includes treating the substrate with a metal organic material and providing a transition metal precursor and a chalcogen precursor around the substrate to synthesize transition metal dichalcogenide on the substrate. The transition metal precursor may include a transition metal element and the chalcogen precursor may include a chalcogen element.