公开(公告)号：US11688813B2

公开(公告)日：2023-06-27

申请号：US17584545

申请日：2022-01-26

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Seung Mo Kang ,  Moon Seung Yang ,  Jongryeol Yoo ,  Sihyung Lee ,  Sunguk Jang ,  Eunhye Choi

IPC: H01L29/786 ,  H01L29/08 ,  H01L29/423 ,  H01L29/06 ,  H01L29/66 ,  H01L29/78 ,  H01L27/088 ,  H01L21/8234 ,  H01L21/311 ,  H01L21/02 ,  H01L21/324

CPC classification number: H01L29/78696 ,  H01L21/02532 ,  H01L21/02636 ,  H01L21/02664 ,  H01L21/311 ,  H01L21/3247 ,  H01L21/823418 ,  H01L21/823437 ,  H01L21/823468 ,  H01L27/0886 ,  H01L29/0673 ,  H01L29/0847 ,  H01L29/42392 ,  H01L29/66545 ,  H01L29/66575 ,  H01L29/785 ,  H01L29/7848

Abstract: A semiconductor device includes a channel pattern including first and second semiconductor patterns stacked on a substrate, a gate electrode covering top and lateral surfaces of the channel pattern and extending in a first direction, and including a first gate segment between the first semiconductor pattern and the second semiconductor pattern, a gate spacer covering a lateral surface of the gate electrode and including an opening exposing the channel pattern, and a first source/drain pattern on a side of the gate spacer and in contact with the channel pattern through the opening, the first source/drain pattern including a sidewall center thickness at a height of the first gate segment and at a center of the opening, and a sidewall edge thickness at the height of the first gate segment and at an edge of the opening, the sidewall edge thickness being about 0.7 to 1 times the sidewall center thickness.

公开(公告)号：US10008575B2

公开(公告)日：2018-06-26

申请号：US15298746

申请日：2016-10-20

Applicant: Samsung Electronics Co., Ltd.

Inventor： Dong Chan Suh ,  Yong Suk Tak ,  Gi Gwan Park ,  Mi Seon Park ,  Moon Seung Yang ,  Seung Hun Lee ,  Poren Tang

IPC: H01L29/423 ,  H01L29/08 ,  H01L29/66 ,  H01L29/78 ,  H01L23/528 ,  H01L29/06

CPC classification number: H01L29/42376 ,  H01L23/5283 ,  H01L29/0673 ,  H01L29/0847 ,  H01L29/42364 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/7831 ,  H01L29/78696

Abstract: A semiconductor device includes at least a first wire pattern, a gate electrode, a semiconductor pattern, a gate insulating layer, and a first spacer. The first wire pattern is on a substrate and isolated from the substrate. The gate electrode surrounds and intersects the first wire pattern. The semiconductor pattern is on both sides of the first wire pattern, and the semiconductor pattern includes a portion which overlaps the first wire pattern. The gate insulating layer is disposed between the gate electrode and the first wire pattern, and the gate insulating layer surrounds the first wire pattern. The first spacer is between the first wire pattern and the substrate, and the first spacer is between the gate insulating layer and the semiconductor pattern.

公开(公告)号：US12142690B2

公开(公告)日：2024-11-12

申请号：US18588163

申请日：2024-02-27

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jung Taek Kim ,  Seok Hoon Kim ,  Pan Kwi Park ,  Moon Seung Yang ,  Seo Jin Jeong ,  Min-Hee Choi ,  Ryong Ha

IPC: H01L29/786 ,  H01L29/06 ,  H01L29/423

Abstract: A semiconductor device includes a multi-channel active pattern, a plurality of gate structures on the multi-channel active pattern and spaced apart from each other in a first direction, the plurality of gate structures including a gate electrode that extends in a second direction different from the first direction, a source/drain recess between the adjacent gate structures, and a source/drain pattern on the multi-channel active pattern in the source/drain recess, wherein the source/drain pattern includes: a semiconductor liner layer including silicon-germanium and extending along the source/drain recess, a semiconductor filling layer including silicon-germanium on the semiconductor liner layer, and at least one or more semiconductor insertion layers between the semiconductor liner layer and the semiconductor filling layer, and wherein the at least one or more semiconductor insertion layers have a saddle structure.

公开(公告)号：US20240194789A1

公开(公告)日：2024-06-13

申请号：US18588163

申请日：2024-02-27

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jung Taek Kim ,  Seok Hoon Kim ,  Pan Kwi Park ,  Moon Seung Yang ,  Seo Jin Jeong ,  Min-Hee Choi ,  Ryong Ha

IPC: H01L29/786 ,  H01L29/06 ,  H01L29/423

CPC classification number: H01L29/78618 ,  H01L29/0665 ,  H01L29/42392 ,  H01L29/78696

Abstract: A semiconductor device includes a multi-channel active pattern, a plurality of gate structures on the multi-channel active pattern and spaced apart from each other in a first direction, the plurality of gate structures including a gate electrode that extends in a second direction different from the first direction, a source/drain recess between the adjacent gate structures, and a source/drain pattern on the multi-channel active pattern in the source/drain recess, wherein the source/drain pattern includes: a semiconductor liner layer including silicon-germanium and extending along the source/drain recess, a semiconductor filling layer including silicon-germanium on the semiconductor liner layer, and at least one or more semiconductor insertion layers between the semiconductor liner layer and the semiconductor filling layer, and wherein the at least one or more semiconductor insertion layers have a saddle structure.

公开(公告)号：US11990552B2

公开(公告)日：2024-05-21

申请号：US17533719

申请日：2021-11-23

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ryong Ha ,  Seok Hoon Kim ,  Jung Taek Kim ,  Pan Kwi Park ,  Moon Seung Yang ,  Seo Jin Jeong

IPC: H01L29/786 ,  H01L29/66 ,  H01L29/423

CPC classification number: H01L29/78618 ,  H01L29/6653 ,  H01L29/66742 ,  H01L29/78696 ,  H01L29/42392

Abstract: A semiconductor device includes an active pattern which includes a lower pattern, and a sheet pattern that is spaced apart from the lower pattern in a first direction, a gate structure on the lower pattern that includes a gate electrode that surrounds the sheet pattern, the gate electrode extending in a second direction that is perpendicular to the first direction, and a source/drain pattern on the lower pattern and in contact with the sheet pattern. A contact surface between the sheet pattern and the source/drain pattern has a first width in the second direction, and the sheet pattern has a second width in the second direction that is greater than the first width.

公开(公告)号：US20220190168A1

公开(公告)日：2022-06-16

申请号：US17519967

申请日：2021-11-05

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jung Taek Kim ,  Seok Hoon Kim ,  Pan Kwi Park ,  Moon Seung Yang ,  Seo Jin Jeong ,  Min-Hee Choi ,  Ryong Ha

IPC: H01L29/786 ,  H01L29/06 ,  H01L29/423

Abstract: A semiconductor device includes a multi-channel active pattern, a plurality of gate structures on the multi-channel active pattern and spaced apart from each other in a first direction, the plurality of gate structures including a gate electrode that extends in a second direction different from the first direction, a source/drain recess between the adjacent gate structures, and a source/drain pattern on the multi-channel active pattern in the source/drain recess, wherein the source/drain pattern includes: a semiconductor liner layer including silicon-germanium and extending along the source/drain recess, a semiconductor filling layer including silicon-germanium on the semiconductor liner layer, and at least one or more semiconductor insertion layers between the semiconductor liner layer and the semiconductor filling layer, and wherein the at least one or more semiconductor insertion layers have a saddle structure.

公开(公告)号：US20220181500A1

公开(公告)日：2022-06-09

申请号：US17533719

申请日：2021-11-23

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ryong Ha ,  Seok Hoon Kim ,  Jung Taek Kim ,  Pan Kwi Park ,  Moon Seung Yang ,  Seo Jin Jeong

IPC: H01L29/786 ,  H01L29/66

Abstract: A semiconductor device includes an active pattern which includes a lower pattern, and a sheet pattern that is spaced apart from the lower pattern in a first direction, a gate structure on the lower pattern that includes a gate electrode that surrounds the sheet pattern, the gate electrode extending in a second direction that is perpendicular to the first direction, and a source/drain pattern on the lower pattern and in contact with the sheet pattern. A contact surface between the sheet pattern and the source/drain pattern has a first width in the second direction, and the sheet pattern has a second width in the second direction that is greater than the first width.

公开(公告)号：US11211457B2

公开(公告)日：2021-12-28

申请号：US16899819

申请日：2020-06-12

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Eunhye Choi ,  Seung Mo Kang ,  Jungtaek Kim ,  Moon Seung Yang ,  Jongryeol Yoo

IPC: H01L29/10 ,  H01L29/08 ,  H01L29/78 ,  H01L29/423 ,  H01L29/66

Abstract: A semiconductor device including an insulating layer on a substrate; channel semiconductor patterns stacked on the insulating layer and vertically spaced apart from each other; a gate electrode crossing the channel semiconductor patterns; source/drain regions respectively at both sides of the gate electrode and connected to each other through the channel semiconductor patterns, the source/drain regions having concave bottom surfaces; and air gaps between the insulating layer and the bottom surfaces of the source/drain regions.