公开(公告)号：US10008575B2

公开(公告)日：2018-06-26

申请号：US15298746

申请日：2016-10-20

Applicant: Samsung Electronics Co., Ltd.

Inventor： Dong Chan Suh ,  Yong Suk Tak ,  Gi Gwan Park ,  Mi Seon Park ,  Moon Seung Yang ,  Seung Hun Lee ,  Poren Tang

IPC: H01L29/423 ,  H01L29/08 ,  H01L29/66 ,  H01L29/78 ,  H01L23/528 ,  H01L29/06

CPC classification number: H01L29/42376 ,  H01L23/5283 ,  H01L29/0673 ,  H01L29/0847 ,  H01L29/42364 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/7831 ,  H01L29/78696

Abstract: A semiconductor device includes at least a first wire pattern, a gate electrode, a semiconductor pattern, a gate insulating layer, and a first spacer. The first wire pattern is on a substrate and isolated from the substrate. The gate electrode surrounds and intersects the first wire pattern. The semiconductor pattern is on both sides of the first wire pattern, and the semiconductor pattern includes a portion which overlaps the first wire pattern. The gate insulating layer is disposed between the gate electrode and the first wire pattern, and the gate insulating layer surrounds the first wire pattern. The first spacer is between the first wire pattern and the substrate, and the first spacer is between the gate insulating layer and the semiconductor pattern.

公开(公告)号：US20170092547A1

公开(公告)日：2017-03-30

申请号：US15234170

申请日：2016-08-11

Applicant: Samsung Electronics Co., Ltd.

Inventor： Poren Tang ,  Sunjung Steve KIM ,  Moon Seung YANG ,  Seung Hun LEE ,  Hyun Jung LEE ,  Geun Hee JEONG

IPC: H01L21/8238 ,  H01L21/306 ,  H01L21/308 ,  H01L29/06 ,  H01L29/16 ,  H01L29/161 ,  H01L29/20 ,  H01L29/10 ,  H01L21/02 ,  H01L27/092

CPC classification number: H01L21/823892 ,  H01L21/02381 ,  H01L21/0245 ,  H01L21/02458 ,  H01L21/02463 ,  H01L21/02499 ,  H01L21/02532 ,  H01L21/0254 ,  H01L21/02546 ,  H01L21/30604 ,  H01L21/30612 ,  H01L21/308 ,  H01L21/823807 ,  H01L21/8258 ,  H01L27/092 ,  H01L29/0653 ,  H01L29/1054 ,  H01L29/1083 ,  H01L29/16 ,  H01L29/161 ,  H01L29/20 ,  H01L29/2003 ,  H01L29/78

Abstract: Methods of fabricating semiconductor device are provided including forming first and second material layers for a first transistor using epitaxial growth processes. A recess region is formed by partially etching the first and second material layers. Third and fourth material layers for a second transistor are formed using epitaxial growth processes.

公开(公告)号：US09899272B2

公开(公告)日：2018-02-20

申请号：US15234170

申请日：2016-08-11

Applicant: Samsung Electronics Co., Ltd.

Inventor： Poren Tang ,  Sunjung Steve Kim ,  Moon Seung Yang ,  Seung Hun Lee ,  Hyun Jung Lee ,  Geun Hee Jeong

IPC: H01L21/8238 ,  H01L21/02 ,  H01L21/306 ,  H01L21/308 ,  H01L29/16 ,  H01L29/161 ,  H01L29/20 ,  H01L29/10 ,  H01L29/06 ,  H01L27/092 ,  H01L21/8258

CPC classification number: H01L21/823892 ,  H01L21/02381 ,  H01L21/0245 ,  H01L21/02458 ,  H01L21/02463 ,  H01L21/02499 ,  H01L21/02532 ,  H01L21/0254 ,  H01L21/02546 ,  H01L21/30604 ,  H01L21/30612 ,  H01L21/308 ,  H01L21/823807 ,  H01L21/8258 ,  H01L27/092 ,  H01L29/0653 ,  H01L29/1054 ,  H01L29/1083 ,  H01L29/16 ,  H01L29/161 ,  H01L29/20 ,  H01L29/2003 ,  H01L29/78

Abstract: Methods of fabricating semiconductor device are provided including forming first and second material layers for a first transistor using epitaxial growth processes. A recess region is formed by partially etching the first and second material layers. Third and fourth material layers for a second transistor are formed using epitaxial growth processes.

公开(公告)号：US09508832B2

公开(公告)日：2016-11-29

申请号：US14749037

申请日：2015-06-24

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyun Jung Lee ,  Bonyoung Koo ,  Sunjung Kim ,  Jongryeol Yoo ,  Seung Hun Lee ,  Poren Tang

IPC: H01L21/306 ,  H01L21/308 ,  H01L21/336 ,  H01L29/66 ,  H01L21/762 ,  H01L21/8238 ,  H01L21/8234

CPC classification number: H01L29/66795 ,  H01L21/3085 ,  H01L21/76224 ,  H01L21/823412 ,  H01L21/823807

Abstract: A method of fabricating a semiconductor device includes forming a channel layer on a substrate, forming a sacrificial layer on the channel layer, forming a hardmask pattern on the sacrificial layer, and performing a patterning process using the hardmask pattern as an etch mask to form a channel portion with an exposed top surface. The channel and sacrificial layers may be formed of silicon germanium, and the sacrificial layer may have a germanium content higher than that of the channel layer.

Abstract translation: 制造半导体器件的方法包括在衬底上形成沟道层，在沟道层上形成牺牲层，在牺牲层上形成硬掩模图案，并使用硬掩模图案作为蚀刻掩模进行图案化处理，形成 通道部分具有​​暴露的顶表面。 通道和牺牲层可由硅锗形成，并且牺牲层的锗含量可高于沟道层的锗含量。