公开(公告)号：US20220157723A1

公开(公告)日：2022-05-19

申请号：US17159972

申请日：2021-01-27

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Saehan Park ,  Hoonseok Seo ,  Jeonghyuk Yim ,  Ki-il Kim ,  Gil Hwan Son

IPC: H01L23/528 ,  H01L27/06 ,  H01L23/48 ,  H01L23/00 ,  H01L21/768 ,  H01L21/822

Abstract: Provided is a semiconductor architecture including a carrier substrate, a landing pad included in the carrier substrate, a first semiconductor device provided on a first surface of the carrier substrate, the first semiconductor device including a first component provided on the landing pad, and a second semiconductor device provided on a second surface of the carrier substrate, a second component protruding from the second semiconductor device being provided on the landing pad.

公开(公告)号：US12183738B2

公开(公告)日：2024-12-31

申请号：US17221355

申请日：2021-04-02

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Seunghyun Song ,  Seungyoung Lee ,  Saehan Park

IPC: H01L27/092 ,  H01L21/822 ,  H01L21/8238 ,  H01L27/06 ,  H01L29/423 ,  H10B10/00

Abstract: A semiconductor device and a method of manufacturing the same are provided. The semiconductor device includes a cross-coupled gate circuit in a three-dimensional (3D) stack including a plurality of transistors, a first gate line of a first transistor among the plurality of transistors connected to a fourth gate line of a fourth transistor among the plurality of transistors, a second gate line of a second transistor among the plurality of transistors connected to a third gate line of a third transistor among the plurality of transistors, a first conductor connecting the first gate line and the fourth gate line, a second conductor connecting the second gate line and the third gate line. The first gate line and the second gate line are arranged above the third gate line and the fourth gate line, respectively.

公开(公告)号：US12144163B2

公开(公告)日：2024-11-12

申请号：US17382060

申请日：2021-07-21

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Byounghak Hong ,  Seunghyun Song ,  Saehan Park ,  Seungyoung Lee ,  Inchan Hwang

IPC: H10B10/00 ,  H01L21/762 ,  H01L27/092 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L29/786

Abstract: A multi-stack semiconductor device includes: a plurality of lower transistor structures arranged on a lower stack and including a plurality of lower fin structures surrounded by a plurality of lower gate structures, respectively; a plurality of upper transistor structures arranged on an upper stack and including a plurality of upper fin structures surrounded by a plurality of upper gate structures, respectively; and at least one of a lower diffusion break structure on the lower stack and a upper diffusion break structure on the upper stack, wherein the lower diffusion break structure is formed between two adjacent lower gate structures, and isolates two lower transistor structures respectively including the two adjacent lower gate structures from each other, and the upper diffusion break structure is formed between two adjacent upper gate structures, and isolates two upper transistor structures respectively including the two adjacent upper gate structures from each other.

公开(公告)号：US11769728B2

公开(公告)日：2023-09-26

申请号：US17159972

申请日：2021-01-27

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Saehan Park ,  Hoonseok Seo ,  Jeonghyuk Yim ,  Ki-il Kim ,  Gil Hwan Son

IPC: H01L23/528 ,  H01L21/768 ,  H01L21/822 ,  H01L23/48 ,  H01L23/00 ,  H01L27/06

CPC classification number: H01L23/5286 ,  H01L21/76898 ,  H01L21/8221 ,  H01L23/481 ,  H01L24/05 ,  H01L27/0694 ,  H01L2224/05025 ,  H01L2224/05147 ,  H01L2224/05157 ,  H01L2224/05176

Abstract: Provided is a semiconductor architecture including a carrier substrate, a landing pad included in the carrier substrate, a first semiconductor device provided on a first surface of the carrier substrate, the first semiconductor device including a first component provided on the landing pad, and a second semiconductor device provided on a second surface of the carrier substrate, a second component protruding from the second semiconductor device being provided on the landing pad.

公开(公告)号：US20230275021A1

公开(公告)日：2023-08-31

申请号：US17738393

申请日：2022-05-06

Applicant: Samsung Electronics Co., Ltd.

Inventor： BYOUNGHAK HONG ,  Jeonghyuk Yim ,  Inchan Hwang ,  Gilhwan Son ,  Seungyoung Lee ,  Saehan Park ,  Janggeun Lee ,  Myunghoon Jung ,  Seungchan Yun ,  Buhyun Ham ,  Kang-ILL Seo

IPC: H01L23/528 ,  H01L23/522 ,  H01L21/302 ,  H01L21/8234

CPC classification number: H01L23/5286 ,  H01L23/5283 ,  H01L23/5226 ,  H01L21/302 ,  H01L21/823475

Abstract: Integrated circuit devices may include a transistor, a passive device, a substrate extending between the transistor and the passive device and a power rail. The passive device may be spaced apart from the substrate. Each of the passive device and the power rail may have a first surface facing the substrate, and the first surface of the passive device is closer than the first surface of the power rail to the substrate.

公开(公告)号：US20220384345A1

公开(公告)日：2022-12-01

申请号：US17389622

申请日：2021-07-30

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Saehan Park ,  Hoonseok Seo ,  Gil Hwan Son ,  Byounghak Hong ,  Kang Ill Seo

IPC: H01L23/528 ,  H01L27/06 ,  H01L23/48 ,  H01L21/768 ,  H01L21/822

Abstract: Provided is a semiconductor architecture including a wafer, a first semiconductor device provided on a first surface of the wafer, the first semiconductor device being configured to route signals, a second semiconductor device provided on a second surface of the wafer opposite to the first surface of the wafer, the second semiconductor device being configured to supply power, and a buried power rail (BPR) included inside of the wafer and extending from the first surface of the wafer to the second surface of the wafer, the BPR being configured to deliver the power from the second semiconductor device to the first semiconductor device.