公开(公告)号：US20250031377A1

公开(公告)日：2025-01-23

申请号：US18602749

申请日：2024-03-12

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Seungyeon Kim ,  Chang-Bum Kim ,  Hyuckjoon Kwon

IPC: H10B43/40 ,  H01L23/00 ,  H01L25/065 ,  H01L25/18 ,  H10B41/27 ,  H10B41/41 ,  H10B43/27 ,  H10B80/00

Abstract: A three-dimensional (3D) semiconductor memory device is provided. The device includes: a memory cell region; and a peripheral circuit configured to control the memory cell region. The memory cell region includes: a cell array region including memory cells arranged vertically along a vertical direction; and a connection region including ends of word lines that are connected to the memory cells, wherein the ends form a stair-step configuration. The peripheral circuit includes a peripheral circuit region overlapping the connection region along the vertical direction. The peripheral circuit region includes a first main pass transistor electrically connected to a first word line of the word lines, and a first dummy pass transistor electrically separated from the word lines. The first main pass transistor and the first dummy pass transistor are arranged along a first direction perpendicular to the vertical direction.

公开(公告)号：US11763879B2

公开(公告)日：2023-09-19

申请号：US17322065

申请日：2021-05-17

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yoonjee Kim ,  Seungyeon Kim ,  Sangwan Nam ,  Hongsoo Jeon ,  Jiho Cho

IPC: G11C11/4097 ,  G11C5/06 ,  G11C11/4093 ,  G11C11/408 ,  G11C11/4099

CPC classification number: G11C11/4097 ,  G11C5/06 ,  G11C11/4085 ,  G11C11/4087 ,  G11C11/4093 ,  G11C11/4099

Abstract: A memory device includes a peripheral circuit area including a first substrate and circuit elements on the first substrate, at least a portion of the circuit elements providing a source driver, and a cell area including a second substrate stacked with the peripheral circuit area in a first direction, perpendicular to an upper surface of the first substrate, and cell blocks and dummy blocks arranged in a second direction, parallel to an upper surface of the second substrate. Each of the cell blocks includes gate electrode layers and insulating layers alternately stacked on the second substrate, and channel structures extending in the first direction to penetrate through the gate electrode layers and the insulating layers and to be connected to the second substrate, at least one source contact block, among the dummy blocks, includes a first dummy insulating region on the second substrate, and source contacts extending in the first direction, penetrating through the first dummy insulating region and connected to the second substrate, and the source contacts are connected to the source driver through metal wirings in an upper portion of the cell area.

公开(公告)号：US11069399B2

公开(公告)日：2021-07-20

申请号：US16840596

申请日：2020-04-06

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Changbum Kim ,  Sunghoon Kim ,  Seungyeon Kim

IPC: G11C11/408 ,  G11C11/4099 ,  G11C5/02 ,  H01L27/24

Abstract: A memory device including a first memory cell array including first memory cells stacked vertically on a first memory cell array region of a top surface of a substrate; a second memory cell array including second memory cells stacked vertically on a second memory cell array region of the top surface; first word lines coupled to the first memory cells and including a subset of first word lines and remaining first word lines; second word lines coupled to the second memory cells and including a subset of second word lines and remaining second word lines; and a row decoder, including a plurality of merge pass transistors each commonly connected to a respective one of the subset of first word lines and a respective one of the subset of second word lines, disposed in a region of the top surface between the first and second cell array regions.

公开(公告)号：US20240105268A1

公开(公告)日：2024-03-28

申请号：US18529897

申请日：2023-12-05

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Seungyeon Kim ,  Daeseok Byeon ,  Pansuk Kwak ,  Hongsoo Jeon

IPC: G11C16/24 ,  G11C5/06 ,  G11C16/26 ,  H10B41/27 ,  H10B43/27

CPC classification number: G11C16/24 ,  G11C5/06 ,  G11C16/26 ,  H10B41/27 ,  H10B43/27

Abstract: A memory device includes: a memory cell array including a first memory block and a second memory block adjacently disposed in a first direction, driving signal lines respectively corresponding to vertically stacked word lines, and a pass transistor circuit including an odd number of pass transistor groups and connected between the driving signal lines and the memory cell array. One of the odd number of pass transistor groups includes a first pass transistor connected between a first word line of the first memory block and a first driving signal line among the driving signal lines, and a second pass transistor connected between a first word line of the second memory block and the first driving signal line adjacently disposed to the first pass transistor in a second direction.

公开(公告)号：US20240049471A1

公开(公告)日：2024-02-08

申请号：US18322040

申请日：2023-05-23

Applicant: Samsung Electronics Co., Ltd.

Inventor： Inho Kang ,  Seungyeon Kim ,  Jiyoung Kim ,  Woosung Yang ,  Jaeeun Lee ,  Kiwhan Song

IPC: H10B43/40 ,  H10B41/10 ,  H10B41/27 ,  H10B41/41 ,  H10B43/10 ,  H10B43/27 ,  H10B80/00 ,  H01L25/065 ,  H01L25/18 ,  H01L23/00

CPC classification number: H10B43/40 ,  H10B41/10 ,  H10B41/27 ,  H10B41/41 ,  H10B43/10 ,  H10B43/27 ,  H10B80/00 ,  H01L25/0657 ,  H01L25/18 ,  H01L24/08 ,  H01L2224/08145 ,  H01L2924/1431 ,  H01L2924/14511

Abstract: A vertically-integrated nonvolatile memory device includes a peripheral circuit structure with a peripheral circuit therein, and cell array structure that is bonded to the peripheral circuit structure, and has a cell area and a connection area therein. The cell area includes a plurality of gate electrodes and a plurality of insulating layers alternately stacked, in the connection area. The plurality of gate electrodes include a cell stack having a staircase shape, a plurality of capacitor core contact structures configured to pass through the cell stack in the cell area, and a plurality of capacitor gate contact structures connected to the plurality of gate electrodes in the connection area. Each of the plurality of capacitor core contact structures includes: (i) a first core conductor electrically connected to the peripheral circuit, and (ii) a first cover insulating layer extending between the first core conductor and the plurality of gate electrodes, and constitutes a capacitor in which the first core conductor, the first cover insulating layer, and the plurality of gate electrodes are connected to the peripheral circuit.

公开(公告)号：US20230267975A1

公开(公告)日：2023-08-24

申请号：US18104533

申请日：2023-02-01

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seungyeon Kim ,  Daeseok Byeon

IPC: G11C7/10 ,  G11C5/06

CPC classification number: G11C7/1039 ,  G11C7/1069 ,  G11C5/063

Abstract: A non-volatile memory device includes a first semiconductor layer including a first cell region in which a first memory cell array is disposed, a second cell region in which a second memory cell array is disposed, wherein the first memory cell array and the second memory cell array each include a plurality of word lines, a plurality of memory cells, and a plurality of bit lines, and a second semiconductor layer including a page buffer circuit region in which a page buffer circuit connected to the first memory cell array and the second memory cell array is disposed, wherein the page buffer circuit region overlaps a boundary region between the first cell region and the second cell region when viewed from the vertical direction.

公开(公告)号：US11462275B2

公开(公告)日：2022-10-04

申请号：US17227501

申请日：2021-04-12

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Seungyeon Kim ,  Daeseok Byeon ,  Pansuk Kwak ,  Hongsoo Jeon

IPC: G11C16/24 ,  G11C5/06 ,  G11C16/26 ,  H01L27/11556 ,  H01L27/11582

Abstract: A memory device includes; a memory cell array including a first memory block and a second memory block adjacently disposed in a first direction, driving signal lines respectively corresponding to vertically stacked word lines, and a pass transistor circuit including an odd number of pass transistor groups and connected between the driving signal lines and the memory cell array. One of the odd number of pass transistor groups includes a first pass transistor connected between a first word line of the first memory block and a first driving signal line among the driving signal lines, and a second pass transistor connected between a first word line of the second memory block and the first driving signal line adjacently disposed to the first pass transistor in a second direction.