中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

31 records (took 0.017 seconds)

    THREE-DIMENSIONAL SEMICONDUCTOR DEVICES AND METHODS OF FABRICATING THE SAME
    11.
    发明申请
    THREE-DIMENSIONAL SEMICONDUCTOR DEVICES AND METHODS OF FABRICATING THE SAME 有权

    公开(公告)号：US20220352203A1

    公开(公告)日：2022-11-03

    申请号：US17859631

    申请日：2022-07-07

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Sunggil Kim ,  Sungjin Kim ,  Seulye Kim ,  Junghwan Kim ,  Chanhyoung Kim

    IPC: H01L27/11582 ,  H01L29/10

    Abstract: A three-dimensional semiconductor device including a conductive layer disposed on a substrate and including a first conductivity-type impurity; an insulating base layer disposed on the conductive layer; a stack structure including a lower insulating film disposed on the insulating base, layer, and a plurality of gate electrodes and a plurality of mold insulating layers alternately stacked on the lower insulating film, wherein the insulating base layer includes a high dielectric material; a vertical structure including a vertical channel layer penetrating through the stack structure arid a vertical insulating layer disposed between the vertical channel layer and the plurality of gate electrodes, the vertical structure having an extended area extending in a width direction in the insulating base layer; and an isolation structure penetrating through the stack structure, the insulating base layer and the conductive layer, and extending in a direction parallel to an upper surface of the substrate, wherein the conductive layer has an extension portion extending along a surface of the vertical channel layer in the extended area of the vertical structure.

    Semiconductor devices and method of manufacturing the same
    12.
    发明授权
    Semiconductor devices and method of manufacturing the same 有权

    公开(公告)号：US11342415B2

    公开(公告)日：2022-05-24

    申请号：US17085467

    申请日：2020-10-30

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Sunggil Kim ,  Kyengmun Kang ,  Juyon Suh ,  Hyeeun Hong

    IPC: H01L29/10 ,  H01L25/07 ,  H01L27/11 ,  H01L23/00 ,  H01L27/11556 ,  H01L27/11582

    Abstract: A semiconductor device, includes: gate electrodes spaced apart from each other and on a substrate; channel structures penetrating the gate electrodes, each of channel structures including a channel layer, a gate dielectric layer between the channel layer and the gate electrodes, a channel insulating layer filling between the channel layers, a channel pad on the channel insulating layer; and separation regions penetrating the gate electrodes, and spaced apart from each other, wherein the gate dielectric layer extends upwardly, further than the channel layer upwardly such that a portion of an inner side surface of the gate dielectric layer contacts the channel pad, the channel pad includes a lower pad on an upper end of the channel layer and the inner side surface of the gate dielectric layer, and having a first recess between the inner side surfaces of the gate dielectric layer; and an upper pad having a first portion in the first recess and a second portion extending from the first portion in a direction, parallel to an upper surface of the substrate on the first portion.

    THREE-DIMENSIONAL SEMICONDUCTOR MEMORY DEVICES
    13.
    发明申请
    THREE-DIMENSIONAL SEMICONDUCTOR MEMORY DEVICES 有权

    公开(公告)号：US20210305276A1

    公开(公告)日：2021-09-30

    申请号：US17076306

    申请日：2020-10-21

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Sunggil Kim ,  Seulye Kim ,  Jung-Hwan Kim

    IPC: H01L27/11582 ,  H01L27/11556

    Abstract: A semiconductor memory device includes a substrate with a cell array region and a connection region, an electrode structure including electrodes stacked on the substrate and having a staircase structure on the connection region, a vertical channel structure on the cell array region to penetrate the electrode structure and electrically connected to the substrate, a dummy structure on the connection region to penetrate the staircase structure, and a first sidewall oxide pattern interposed between the substrate and the dummy structure. The dummy structure includes an upper portion that is on the substrate, a middle portion that is in contact with the first sidewall oxide pattern, and a lower portion that is below the middle portion. With increasing vertical distance from the upper portion, a diameter of the middle portion decreases until it reaches its smallest value and then increases.

    Semiconductor devices and method of manufacturing the same
    15.
    发明授权
    Semiconductor devices and method of manufacturing the same 有权

    公开(公告)号：US11764268B2

    公开(公告)日：2023-09-19

    申请号：US17749719

    申请日：2022-05-20

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Sunggil Kim ,  Kyengmun Kang ,  Juyon Suh ,  Hyeeun Hong

    IPC: H01L29/10 ,  H01L25/07 ,  H01L23/00 ,  H10B41/27 ,  H10B43/27

    CPC classification number: H01L29/1037 ,  H01L24/08 ,  H01L25/074 ,  H01L2224/08146 ,  H10B41/27 ,  H10B43/27

    Abstract: A semiconductor device, includes: gate electrodes spaced apart from each other and on a substrate; channel structures penetrating the gate electrodes, each of channel structures including a channel layer, a gate dielectric layer between the channel layer and the gate electrodes, a channel insulating layer filling between the channel layers, a channel pad on the channel insulating layer; and separation regions penetrating the gate electrodes, and spaced apart from each other, wherein the gate dielectric layer extends upwardly, further than the channel layer upwardly such that a portion of an inner side surface of the gate dielectric layer contacts the channel pad, the channel pad includes a lower pad on an upper end of the channel layer and the inner side surface of the gate dielectric layer, and having a first recess between the inner side surfaces of the gate dielectric layer; and an upper pad having a first portion in the first recess and a second portion extending from the first portion in a direction, parallel to an upper surface of the substrate on the first portion.

    Three-dimensional semiconductor memory devices
    16.
    发明授权
    Three-dimensional semiconductor memory devices 有权

    公开(公告)号：US11711920B2

    公开(公告)日：2023-07-25

    申请号：US17076306

    申请日：2020-10-21

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Sunggil Kim ,  Seulye Kim ,  Jung-Hwan Kim

    IPC: H01L27/11582 ,  H10B43/27 ,  H10B41/27 ,  H01L21/02

    CPC classification number: H10B43/27 ,  H10B41/27 ,  H01L21/02233

    Abstract: A semiconductor memory device includes a substrate with a cell array region and a connection region, an electrode structure including electrodes stacked on the substrate and having a staircase structure on the connection region, a vertical channel structure on the cell array region to penetrate the electrode structure and electrically connected to the substrate, a dummy structure on the connection region to penetrate the staircase structure, and a first sidewall oxide pattern interposed between the substrate and the dummy structure. The dummy structure includes an upper portion that is on the substrate, a middle portion that is in contact with the first sidewall oxide pattern, and a lower portion that is below the middle portion. With increasing vertical distance from the upper portion, a diameter of the middle portion decreases until it reaches its smallest value and then increases.

    Vertical semiconductor devices
    17.
    发明授权
    Vertical semiconductor devices 有权

    公开(公告)号：US11430800B2

    公开(公告)日：2022-08-30

    申请号：US16839184

    申请日：2020-04-03

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Sunggil Kim ,  Seulye Kim ,  Dongkyum Kim ,  Sungjin Kim ,  Junghwan Kim ,  Chanhyoung Kim ,  Jihoon Choi

    IPC: H01L27/11582 ,  H01L27/11556 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11558

    Abstract: A vertical semiconductor device may include a stacked structure, a channel structure and a lower connection structure. The stacked structure may include insulation layers and gate electrodes alternately repeatedly stacked. The stacked structure may be spaced apart from an upper surface of a substrate. The channel structure may include a charge storage structure and a channel. The channel structure may pass through the stacked structure. The lower connection structure may be formed on the substrate. The lower connection structure may be electrically connected with the channel and the substrate. A sidewall of the lower connection structure may include a protrusion disposed at a central portion of the sidewall from the upper surface of the substrate in a vertical direction. The vertical semiconductor device may have a high reliability.

Patent Agency Ranking