公开(公告)号：US20240105842A1

公开(公告)日：2024-03-28

申请号：US18456934

申请日：2023-08-28

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sunghwan JANG ,  Dohee KIM ,  Pyung MOON ,  Sunguk JANG ,  Mina SEOL

IPC: H01L29/78 ,  H01L21/02 ,  H01L21/308 ,  H01L29/40

CPC classification number: H01L29/7827 ,  H01L21/02532 ,  H01L21/308 ,  H01L29/401

Abstract: In a method of manufacturing a semiconductor device, a first selective epitaxial growth (SEG) process is performed on a substrate to form a first channel. A first etching process is performed to form a first recess through the first channel and an upper portion of the substrate. A sidewall of the first channel exposed by the first recess is slanted with respect to an upper surface of the substrate. A second SEG process is performed to form a second channel on a surface of the substrate and the sidewall of the first channel exposed by the first recess. A gate structure is formed to fill the first recess. An impurity region is formed at an upper portion of the substrate adjacent to the gate structure.

公开(公告)号：US20230137340A1

公开(公告)日：2023-05-04

申请号：US17858150

申请日：2022-07-06

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Dohee KIM ,  Sunguk JANG ,  Sahwan HONG ,  Kongsoo LEE

IPC: H01L27/108

Abstract: A pattern formation method includes forming a first capping layer on a substrate, forming a recess that penetrates the first capping layer and an upper portion of the substrate, such that a non-penetrated portion of the first capping layer constitutes a first capping pattern, forming a second capping pattern that covers an inner sidewall of the recess, and forming a stack structure in the recess, such that the stack structure includes first stack patterns and second stack patterns that are alternately stacked, and the second capping pattern is between the substrate and a lateral surface of the stack structure.

公开(公告)号：US20220005958A1

公开(公告)日：2022-01-06

申请号：US17480457

申请日：2021-09-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sunguk JANG ,  Kihwan KIM ,  Sujin JUNG ,  Youngdae CHO

IPC: H01L29/786 ,  H01L29/08 ,  H01L29/423 ,  H01L29/78 ,  H01L29/06 ,  H01L29/66

Abstract: A semiconductor device includes an active region on a substrate extending in a first direction, the active region having an upper surface and sidewalls, a plurality of channel layers above the active region to be vertically spaced apart from each other, a gate electrode extending in a second direction to intersect the active region and partially surrounding the plurality of channel layers, and a source/drain region on the active region on at least one side of the gate electrode and in contact with the plurality of channel layers, and extending from the sidewalls of the active region having a major width in the second direction in a first region adjacent to a lowermost channel layer adjacent to the active region among the plurality of channel layer.

公开(公告)号：US20240057321A1

公开(公告)日：2024-02-15

申请号：US18338711

申请日：2023-06-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： Daejin NAM ,  Boreum LEE ,  Kongsoo LEE ,  Sunguk JANG

IPC: H10B12/00

CPC classification number: H10B12/482 ,  H10B12/315 ,  H10B12/485 ,  H10B12/02

Abstract: A semiconductor device may include a substrate including an active pattern, a conductive filling pattern on an impurity region at an upper portion of the active pattern, a first spacer and a second spacer stacked on a sidewall of the conductive filling pattern in a horizontal direction, and a bit line structure on the conductive filling pattern. The impurity region may include impurities. The horizontal direction may be parallel to an upper surface of the substrate. The first spacer may include an insulating material containing the impurities.

公开(公告)号：US20240006190A1

公开(公告)日：2024-01-04

申请号：US18117864

申请日：2023-03-06

Applicant: SAMSUNG ELECTRONICS CO., LTD

Inventor： Jin-Hong PARK ,  Hogeun AHN ,  BoReum LEE ,  Sunguk JANG ,  Jiwan KOO ,  Seunghwan SEO

IPC: H01L21/467 ,  H01L29/66 ,  H01L21/441

CPC classification number: H01L21/467 ,  H01L29/66969 ,  H01L21/441

Abstract: A method of manufacturing a semiconductor device includes forming a channel layer on a substrate, forming a mask on the channel layer, surface-treating an exposed surface of the channel layer exposed from the mask, forming an electrode on the exposed surface of the channel layer, and removing the mask. The channel layer includes a two-dimensional material, and the surface-treating of the exposed surface of the channel layer includes surface-treating the exposed surface of the channel layer with HCl.

公开(公告)号：US20230307498A1

公开(公告)日：2023-09-28

申请号：US18205671

申请日：2023-06-05

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sujin JUNG ,  Kihwan KIM ,  Sunguk JANG ,  Youngdae CHO

IPC: H01L29/10 ,  H01L29/16 ,  H01L29/06 ,  H01L29/78 ,  H01L29/08 ,  H01L29/423 ,  H01L29/786

CPC classification number: H01L29/1037 ,  H01L29/1608 ,  H01L29/0653 ,  H01L29/785 ,  H01L29/0847 ,  H01L29/0665 ,  H01L29/42392 ,  H01L29/78696

Abstract: A semiconductor device including: an active pattern on a substrate, the active pattern including a recess, the recess having a “V” shape; a growth prevention pattern on the recess; gate structures on portions of the active pattern at opposite sides of the recess; channels spaced apart from each other in a vertical direction perpendicular to an upper surface of the substrate, each of the channels extending through one of the gate structures; and a source/drain layer on the growth prevention pattern, the source/drain layer contacting the channels.

公开(公告)号：US20220216348A1

公开(公告)日：2022-07-07

申请号：US17489181

申请日：2021-09-29

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Kihwan KIM ,  Sunguk JANG ,  Sujin JUNG ,  Youngdae CHO

IPC: H01L29/786 ,  H01L29/06 ,  H01L29/167 ,  H01L29/423 ,  H01L21/02 ,  H01L29/66

Abstract: A semiconductor device includes an active region extending in a first direction on a substrate, a plurality of channel layers vertically spaced apart from each other on the active region and including a semiconductor material, a gate structure extending in a second direction on the substrate, and a source/drain region disposed on the active region on at least one side of the gate structure. The gate structure intersects the active region and the plurality of channel layers, and surrounds the plurality of channel layers. The source/drain region contacts the plurality of channel layers and includes first impurities. In at least a portion of the plurality of channel layers, a lower region adjacent to the active region includes the first impurities and second impurities at a first concentration, and an upper region includes the first impurities and the second impurities at a second concentration lower than the first concentration.

公开(公告)号：US20200075764A1

公开(公告)日：2020-03-05

申请号：US16412796

申请日：2019-05-15

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sunguk JANG ,  Sujin JUNG ,  Jinyeong JOE ,  Jeongho YOO ,  Seung Hun LEE ,  Jongryeol YOO

IPC: H01L29/78 ,  H01L29/417 ,  H01L29/66 ,  H01L29/08 ,  H01L29/10 ,  H01L27/088

Abstract: A semiconductor device includes a first active fin protruding from a substrate, a first gate pattern covering a side surface and a top surface of the first active fin, and first source/drain patterns at opposite sides of the first gate pattern, each of the first source/drain patterns including a first lower side and a second lower side spaced apart from each other, a first upper side extended from the first lower side, a second upper side extended from the second lower side. The first lower side may be inclined at a first angle relative to a top surface of the substrate, the second upper side may be inclined at a second angle relative to the top surface of the substrate, and the first angle may be greater than the second angle.