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公开(公告)号：US20220199618A1
公开(公告)日：2022-06-23
申请号：US17383749
申请日：2021-07-23
发明人： Sujin JUNG , Kihwan KIM , Sunguk JANG , Youngdae CHO
IPC分类号： H01L27/088 , H01L29/06 , H01L29/78
摘要： An integrated circuit (IC) device includes a fin-type active region extending longitudinally in a first lateral direction on a substrate. A nanosheet is apart from a fin top surface of the fin-type active region in a vertical direction. An inner insulating spacer is between the substrate and the nanosheet. A gate line includes a main gate portion and a sub-gate portion. The main gate portion extends longitudinally in a second lateral direction on the nanosheet. The sub-gate portion is integrally connected to the main gate portion and between the substrate and the nanosheet. A source/drain region is in contact with the inner insulating spacer and the nanosheet. The source/drain region includes a single crystalline semiconductor body and at least one lower stacking fault surface linearly extending from the inner insulating spacer through the single crystalline semiconductor body.
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公开(公告)号：US20220115514A1
公开(公告)日：2022-04-14
申请号：US17559347
申请日：2021-12-22
发明人： Sujin JUNG , Kihwan KIM , Sunguk JANG , Youngdae CHO
IPC分类号： H01L29/423 , H01L29/786 , H01L29/06 , H01L29/08
摘要： A semiconductor device including: an active pattern on a substrate, the active pattern including a recess, the recess having a “V” shape; a growth prevention pattern on the recess; gate structures on portions of the active pattern at opposite sides of the recess; channels spaced apart from each other in a vertical direction perpendicular to an upper surface of the substrate, each of the channels extending through one of the gate structures; and a source/drain layer on the growth prevention pattern, the source/drain layer contacting the channels.
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公开(公告)号：US20200381564A1
公开(公告)日：2020-12-03
申请号：US16774653
申请日：2020-01-28
发明人： Seung Mo KANG , Moon Seung YANG , Jongryeol YOO , Sihyung LEE , Sunguk JANG , Eunhye CHOI
IPC分类号： H01L29/786 , H01L29/423 , H01L29/08
摘要： A semiconductor device includes a channel pattern including first and second semiconductor patterns stacked on a substrate, a gate electrode covering top and lateral surfaces of the channel pattern and extending in a first direction, and including a first gate segment between the first semiconductor pattern and the second semiconductor pattern, a gate spacer covering a lateral surface of the gate electrode and including an opening exposing the channel pattern, and a first source/drain pattern on a side of the gate spacer and in contact with the channel pattern through the opening, the first source/drain pattern including a sidewall center thickness at a height of the first gate segment and at a center of the opening, and a sidewall edge thickness at the height of the first gate segment and at an edge of the opening, the sidewall edge thickness being about 0.7 to 1 times the sidewall center thickness.
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公开(公告)号：US20240196602A1
公开(公告)日：2024-06-13
申请号：US18490212
申请日：2023-10-19
发明人： Wonhee CHOI , Daejin NAM , Sunguk JANG
IPC分类号： H10B12/00 , H01L29/423
CPC分类号： H10B12/485 , H01L29/42356 , H10B12/482 , H10B12/488
摘要： An integrated circuit device includes a substrate having an active region, a word line extending in the substrate in a first horizontal direction, a bit line extending on the word line in a second horizontal direction, a bit line contact electrically connecting the bit line to the active region, a doping contact connecting the bit line contact to the active region, a cell pad having a horizontal width greater than that of the active region, a buried contact that digs into one side wall of the cell pad, and a conductive landing pad facing the bit line in the first horizontal direction. The doping contact includes a first doping contact and a second doping contact, and a thickness of the first doping contact in the vertical direction is less than that of the second doping contact in the vertical direction.
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公开(公告)号：US20220149210A1
公开(公告)日：2022-05-12
申请号：US17584545
申请日：2022-01-26
发明人： Seung Mo KANG , Moon Seung YANG , Jongryeol YOO , Sihyung LEE , Sunguk JANG , Eunhye CHOI
IPC分类号： H01L29/786 , H01L29/08 , H01L29/423 , H01L29/06 , H01L29/66 , H01L29/78 , H01L27/088 , H01L21/8234 , H01L21/311
摘要： A semiconductor device includes a channel pattern including first and second semiconductor patterns stacked on a substrate, a gate electrode covering top and lateral surfaces of the channel pattern and extending in a first direction, and including a first gate segment between the first semiconductor pattern and the second semiconductor pattern, a gate spacer covering a lateral surface of the gate electrode and including an opening exposing the channel pattern, and a first source/drain pattern on a side of the gate spacer and in contact with the channel pattern through the opening, the first source/drain pattern including a sidewall center thickness at a height of the first gate segment and at a center of the opening, and a sidewall edge thickness at the height of the first gate segment and at an edge of the opening, the sidewall edge thickness being about 0.7 to 1 times the sidewall center thickness.
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公开(公告)号：US20240105842A1
公开(公告)日：2024-03-28
申请号：US18456934
申请日：2023-08-28
发明人： Sunghwan JANG , Dohee KIM , Pyung MOON , Sunguk JANG , Mina SEOL
IPC分类号： H01L29/78 , H01L21/02 , H01L21/308 , H01L29/40
CPC分类号： H01L29/7827 , H01L21/02532 , H01L21/308 , H01L29/401
摘要： In a method of manufacturing a semiconductor device, a first selective epitaxial growth (SEG) process is performed on a substrate to form a first channel. A first etching process is performed to form a first recess through the first channel and an upper portion of the substrate. A sidewall of the first channel exposed by the first recess is slanted with respect to an upper surface of the substrate. A second SEG process is performed to form a second channel on a surface of the substrate and the sidewall of the first channel exposed by the first recess. A gate structure is formed to fill the first recess. An impurity region is formed at an upper portion of the substrate adjacent to the gate structure.
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公开(公告)号：US20230137340A1
公开(公告)日：2023-05-04
申请号：US17858150
申请日：2022-07-06
发明人： Dohee KIM , Sunguk JANG , Sahwan HONG , Kongsoo LEE
IPC分类号： H01L27/108
摘要： A pattern formation method includes forming a first capping layer on a substrate, forming a recess that penetrates the first capping layer and an upper portion of the substrate, such that a non-penetrated portion of the first capping layer constitutes a first capping pattern, forming a second capping pattern that covers an inner sidewall of the recess, and forming a stack structure in the recess, such that the stack structure includes first stack patterns and second stack patterns that are alternately stacked, and the second capping pattern is between the substrate and a lateral surface of the stack structure.
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公开(公告)号：US20220005958A1
公开(公告)日：2022-01-06
申请号：US17480457
申请日：2021-09-21
发明人： Sunguk JANG , Kihwan KIM , Sujin JUNG , Youngdae CHO
IPC分类号： H01L29/786 , H01L29/08 , H01L29/423 , H01L29/78 , H01L29/06 , H01L29/66
摘要： A semiconductor device includes an active region on a substrate extending in a first direction, the active region having an upper surface and sidewalls, a plurality of channel layers above the active region to be vertically spaced apart from each other, a gate electrode extending in a second direction to intersect the active region and partially surrounding the plurality of channel layers, and a source/drain region on the active region on at least one side of the gate electrode and in contact with the plurality of channel layers, and extending from the sidewalls of the active region having a major width in the second direction in a first region adjacent to a lowermost channel layer adjacent to the active region among the plurality of channel layer.
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公开(公告)号：US20240057321A1
公开(公告)日：2024-02-15
申请号：US18338711
申请日：2023-06-21
发明人： Daejin NAM , Boreum LEE , Kongsoo LEE , Sunguk JANG
IPC分类号： H10B12/00
CPC分类号： H10B12/482 , H10B12/315 , H10B12/485 , H10B12/02
摘要： A semiconductor device may include a substrate including an active pattern, a conductive filling pattern on an impurity region at an upper portion of the active pattern, a first spacer and a second spacer stacked on a sidewall of the conductive filling pattern in a horizontal direction, and a bit line structure on the conductive filling pattern. The impurity region may include impurities. The horizontal direction may be parallel to an upper surface of the substrate. The first spacer may include an insulating material containing the impurities.
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公开(公告)号：US20240006190A1
公开(公告)日：2024-01-04
申请号：US18117864
申请日：2023-03-06
发明人： Jin-Hong PARK , Hogeun AHN , BoReum LEE , Sunguk JANG , Jiwan KOO , Seunghwan SEO
IPC分类号： H01L21/467 , H01L29/66 , H01L21/441
CPC分类号： H01L21/467 , H01L29/66969 , H01L21/441
摘要： A method of manufacturing a semiconductor device includes forming a channel layer on a substrate, forming a mask on the channel layer, surface-treating an exposed surface of the channel layer exposed from the mask, forming an electrode on the exposed surface of the channel layer, and removing the mask. The channel layer includes a two-dimensional material, and the surface-treating of the exposed surface of the channel layer includes surface-treating the exposed surface of the channel layer with HCl.
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