公开(公告)号：US20220069129A1

公开(公告)日：2022-03-03

申请号：US17321960

申请日：2021-05-17

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Geunwoo KIM ,  Wandon KIM ,  Heonbok LEE ,  Yoontae HWANG

IPC: H01L29/78 ,  H01L29/417

Abstract: A semiconductor device includes: a fin-type active region extending on a substrate in a first direction; a gate structure extending across the fin-type active region in a second direction, different from the first direction; a source/drain region in the fin-type active region on one side of the gate structure; and first and second contact structures connected to the source/drain region and the gate structure, respectively, wherein at least one of the first and second contact structures includes a seeding layer on at least one of the gate structure and the source/drain region and including a first crystalline metal, and a contact plug on the seeding layer and including a second crystalline metal different from the first crystalline metal, and the second crystalline metal is substantially lattice-matched to the first crystalline metal at an interface between the seeding layer and the contact plug.

公开(公告)号：US20240234312A1

公开(公告)日：2024-07-11

申请号：US18615177

申请日：2024-03-25

Applicant: Samsung Electronics Co., Ltd.

Inventor： Euibok LEE ,  Wandon KIM

IPC: H01L23/528 ,  H01L21/311 ,  H01L21/768

CPC classification number: H01L23/528 ,  H01L21/31144 ,  H01L21/76802 ,  H01L21/76877

Abstract: An integrated circuit (IC) device includes a first conductive line in a closed curve defining a local area on a substrate. The first conductive line has a first end portion and a second end portion. A second conductive line is outside the local area. The second conductive line has a linear line portion along the closed curve and a bulging end portion along the closed curve. The bulging end portion protrudes from the linear line portion toward the first end portion of the first conductive line in the second lateral direction and protrudes further than the first end portion to the outside of the local area. A method of manufacturing an IC device includes forming a first reference pattern having a mandrel hole. A reference spacer is formed inside the mandrel hole. A second reference pattern is formed. The second reference pattern has a shift hole.

公开(公告)号：US20240128335A1

公开(公告)日：2024-04-18

申请号：US18369236

申请日：2023-09-18

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Junggun YOU ,  Junki PARK ,  Sunghwan KIM ,  Wandon KIM ,  Sughyun SUNG ,  Hyunbae LEE

IPC: H01L29/417 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775 ,  H01L29/786

CPC classification number: H01L29/41733 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/66545 ,  H01L29/775 ,  H01L29/78696

Abstract: A semiconductor device includes an active region on a substrate, a plurality of channel layers spaced apart from each other, a gate structure on the substrate, a source/drain region on at least one side of the gate structure, and a contact plug connected to the source/drain region. The contact plug includes a metal-semiconductor compound layer and a barrier layer on the metal-semiconductor compound layer. The contact plug includes a first inclined surface and a second inclined surface positioned where the metal-semiconductor compound layer and the barrier layer directly contact each other. The barrier layer includes first and second ends protruding towards the gate structure. The first and second ends are positioned at a level higher than an upper surface of an uppermost channel layer. An uppermost portion of the metal-semiconductor compound layer is positioned at a level higher than an upper surface of the source/drain region.

公开(公告)号：US20220352156A1

公开(公告)日：2022-11-03

申请号：US17846177

申请日：2022-06-22

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sunyoung NOH ,  Wandon KIM ,  Hyunbae LEE ,  Donggon YOO ,  Dong-Chan LIM

IPC: H01L27/088 ,  H01L23/528 ,  H01L23/532 ,  H01L29/06 ,  H01L21/321 ,  H01L21/768 ,  H01L21/8234 ,  H01L23/535

Abstract: A semiconductor device includes an interlayer dielectric layer on a substrate, a first connection line that fills a first trench of the interlayer dielectric layer, the first trench having a first width, and a second connection line that fills a second trench of the interlayer dielectric layer, the second trench having a second width greater than the first width, and the second connection line including a first metal layer that covers an inner sidewall of the second trench, a barrier layer that covers a bottom surface of the second trench, and a second metal layer on the first metal layer and the barrier layer, the first connection line and the first metal layer include a first metal, and the second metal layer includes a second metal different from the first metal.

公开(公告)号：US20220157954A1

公开(公告)日：2022-05-19

申请号：US17588670

申请日：2022-01-31

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yoon Tae HWANG ,  Wandon KIM ,  Geunwoo KIM

IPC: H01L29/417 ,  H01L21/768 ,  H01L23/532 ,  H01L29/08 ,  H01L21/285 ,  H01L29/45

Abstract: A semiconductor device including a lower contact pattern including a first metal, an upper contact pattern including a second metal, a first resistivity of first metal being greater than a second resistivity of the second metal, and a metal barrier layer between the lower contact pattern and a lower portion of the upper contact pattern, the metal barrier layer including a third metal, the third metal being different from the first and second metals may be provided. A lower width of the upper contact pattern may be less than an upper width of the lower contact pattern.

公开(公告)号：US20220109057A1

公开(公告)日：2022-04-07

申请号：US17245601

申请日：2021-04-30

Applicant: Samsung Electronics Co., Ltd.

Inventor： Munhyeon KIM ,  Myung Gil KANG ,  Wandon KIM

IPC: H01L29/423 ,  H01L29/06 ,  H01L29/49 ,  H01L29/51 ,  H01L29/786 ,  H01L29/78 ,  H01L27/092 ,  H01L29/66 ,  H01L29/40

Abstract: Disclosed are a semiconductor device and a method of fabricating the same. The device may include a substrate, an active pattern in an upper portion of the substrate and is extending in a first direction, a gate electrode crossing the active pattern and extending in a second direction intersecting the first direction, a first gate spacer covering a side surface of the gate electrode, a first inhibition layer between the gate electrode and the first gate spacer, and a gate insulating layer between the gate electrode and the active pattern. The gate insulating layer may include a high-k dielectric layer and a gate oxide layer. The gate oxide layer may be between the high-k dielectric layer and the active pattern. The high-k dielectric layer may be between the gate oxide layer and the gate electrode.

公开(公告)号：US20190198498A1

公开(公告)日：2019-06-27

申请号：US16116295

申请日：2018-08-29

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jongho PARK ,  Wandon KIM ,  Jeonghyuk YIM ,  Sangjin HYUN

IPC: H01L27/092 ,  H01L29/49 ,  H01L21/8238

Abstract: A semiconductor device includes first, second, and third transistors on a substrate and having different threshold voltages from each other, each of the first, second, and third transistors including: a gate insulating layer, a first work function metal layer, and a second work function metal layer. The first work function metal layer of the first transistor may include a first sub-work function layer, the first work function metal layer of the second transistor may include a second sub-work function layer, the first work function metal layer of the third transistor may include a third sub-work function layer, and the first, second, and third sub-work function layers may have different work functions from each other.

公开(公告)号：US20250096134A1

公开(公告)日：2025-03-20

申请号：US18650288

申请日：2024-04-30

Applicant: Samsung Electronics Co., Ltd.

Inventor： Geunwoo KIM ,  Hyunwoo KANG ,  Mingyu KIM ,  Wandon KIM ,  Wonkeun CHUNG ,  Hyoseok CHOI

IPC: H01L23/528 ,  H01L23/522 ,  H01L27/092 ,  H01L29/06 ,  H01L29/417 ,  H01L29/423 ,  H01L29/775 ,  H01L29/78 ,  H01L29/786

Abstract: An integrated circuit device may include a source/drain contact insulation layer on a lower structure, a source/drain contact via penetrating through the source/drain contact insulation layer, an interconnect wiring insulation layer on the source/drain contact insulation layer and including an interconnect wiring trench exposing a top surface of the source/drain contact via, a first interconnect wiring layer covering a lower portion of a sidewall of the interconnect wiring trench and including a first precursor, and a second interconnect wiring layer on the first interconnect wiring layer. The second interconnect wiring layer may cover an upper portion of a sidewall of the interconnect wiring trench and may include a second precursor. A crystal grain size of the second precursor may be larger than a crystal grain size of the first precursor.

公开(公告)号：US20230118906A1

公开(公告)日：2023-04-20

申请号：US18085871

申请日：2022-12-21

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Yoontae HWANG ,  Wandon KIM ,  Geunwoo KIM ,  Heonbok LEE ,  Taegon KIM ,  Hanki LEE

IPC: H01L29/45 ,  H01L29/78 ,  H01L29/66 ,  H01L29/417 ,  H01L21/285 ,  H01L29/08 ,  H01L23/532 ,  H01L23/485 ,  H01L23/522

Abstract: A semiconductor device including a substrate; a fin active region on the substrate and extending in a first direction; a gate structure extending across the fin active region and extending in a second direction; a source/drain region in the fin active region on a side of the gate structure; an insulating structure covering the gate structure and the source/drain region; and contact structures penetrating through the insulating structure and respectively connected to the source/drain region and the gate structure, wherein one of the contact structures includes a seed layer on the gate structure or the source/drain regions and including lower and upper regions, the lower region having a first grain size and the upper region being amorphous or having a grain size different from the first grain size, and a contact plug on an upper region of the seed layer and having a second grain size.

公开(公告)号：US20230012516A1

公开(公告)日：2023-01-19

申请号：US17672033

申请日：2022-02-15

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yoontae HWANG ,  Geunwoo KIM ,  Wandon KIM ,  Hyunbae LEE

IPC: H01L29/417 ,  H01L29/45 ,  H01L23/522

Abstract: An integrated circuit (IC) device includes a conductive region including a first metal on a substrate. An insulating film is on the conductive region. A conductive plug including a second metal passes through the insulating film and extends in a vertical direction. A conductive barrier pattern is between the conductive region and the conductive plug. The conductive barrier pattern has a first surface in contact with the conductive region and a second surface in contact with the conductive plug. A bottom surface and a lower sidewall of the conductive plug are in contact with the conductive barrier pattern, and an upper sidewall of the conductive plug is in contact with the insulating film. The conductive barrier pattern includes a vertical barrier portion between the insulating film and the conductive plug, and the vertical barrier portion has a width tapering along a first direction away from the conductive region.