-
公开(公告)号：US12066893B2
公开(公告)日：2024-08-20
申请号：US18226622
申请日：2023-07-26
Applicant: Samsung Electronics Co., Ltd.
Inventor： Sungrae Kim , Kijun Lee , Myungkyu Lee , Yeonggeol Song , Jinhoon Jang , Sunghye Cho , Isak Hwang
CPC classification number: G06F11/1068
Abstract: A semiconductor memory device includes a memory cell array, a link error correction code (ECC) engine and on-die ECC engine. The memory cell array includes a plurality of volatile memory cells. The link ECC engine provides a main data by performing a first ECC decoding on a first codeword including the main data and a first parity data, and generates a first error flag based on a result of the first ECC decoding. The on-die ECC engine generates a second parity data by performing a first ECC encoding on the main data, provides a target page of the memory cell array with a second codeword including the main data and the second parity data in response to the first error flag being deactivated or generates a third codeword by changing at least one of bits of the second codeword in response to the first error flag being deactivated.
-
公开(公告)号：US20240096391A1
公开(公告)日：2024-03-21
申请号：US18341128
申请日：2023-06-26
Applicant: Samsung Electronics Co., Ltd.
Inventor： Sunghye Cho , Kijun Lee , Eunae Lee , Kyomin Sohn , Yeonggeol Song , Myungkyu Lee
IPC: G11C11/406
CPC classification number: G11C11/406
Abstract: A memory device includes a memory cell array having a plurality of rows of memory cells therein, and a row hammer managing circuit, which is configured to detect a row hammer address based on a pre row hammer address, and each of a plurality of input row addresses associated with a plurality of accesses during a monitoring period for monitoring the plurality of accesses to a plurality of the rows of memory cells. A refresh control circuit is provided and is configured to perform a refresh operation on a memory cell row physically adjacent to a memory cell row corresponding to the row hammer address.
-
公开(公告)号：US11762736B2
公开(公告)日：2023-09-19
申请号：US17580048
申请日：2022-01-20
Applicant: Samsung Electronics Co., Ltd.
Inventor： Sungrae Kim , Kijun Lee , Myungkyu Lee , Yeonggeol Song , Jinhoon Jang , Sunghye Cho , Isak Hwang
CPC classification number: G06F11/1068
Abstract: A semiconductor memory device includes a memory cell array, a link error correction code (ECC) engine and on-die ECC engine. The memory cell array includes a plurality of volatile memory cells. The link ECC engine provides a main data by performing a first ECC decoding on a first codeword including the main data and a first parity data, and generates a first error flag based on a result of the first ECC decoding. The on-die ECC engine generates a second parity data by performing a first ECC encoding on the main data, provides a target page of the memory cell array with a second codeword including the main data and the second parity data in response to the first error flag being deactivated or generates a third codeword by changing at least one of bits of the second codeword in response to the first error flag being deactivated.
-
公开(公告)号：US11681458B2
公开(公告)日：2023-06-20
申请号：US17090726
申请日：2020-11-05
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Sunghye Cho , Kijun Lee , Sung-Rae Kim , Chanki Kim , Yeonggeol Song , Yesin Ryu , Jaeyoun Youn , Myungkyu Lee
CPC classification number: G06F3/0655 , G06F3/0619 , G06F3/0673 , G06F11/1048 , G11C29/52
Abstract: A method for reading data from a memory includes; reading a codeword from the memory cells, correcting the errors when a number of errors in the codeword is less than a maximum number of correctable errors, correcting the errors when the number of errors in the codeword is equal to the maximum number of correctable errors and the errors correspond to a same sub-word line, and outputting signal indicating that the errors are an uncorrectable error when the number of errors of the codeword is equal to the maximum number of correctable errors and the errors correspond to different sub-word lines.
-
公开(公告)号：US20220374309A1
公开(公告)日：2022-11-24
申请号：US17580048
申请日：2022-01-20
Applicant: Samsung Electronics Co., Ltd.
Inventor： Sungrae Kim , Kijun Lee , Myungkyu Lee , Yeonggeol Song , Jinhoon Jang , Sunghye Cho , Isak Hwang
IPC: G06F11/10
Abstract: A semiconductor memory device includes a memory cell array, a link error correction code (ECC) engine and on-die ECC engine. The memory cell array includes a plurality of volatile memory cells. The link ECC engine provides a main data by performing a first ECC decoding on a first coedword including the main data and a first parity data, and generates a first error flag based on a result of the first ECC decoding. The on-die ECC engine generates a second parity data by performing a first ECC encoding on the main data, provides a target page of the memory cell array with a second codeword including the main data and the second parity data in response to the first error flag being deactivated or generates a third codeword by changing at least one of bits of the second codeword in response to the first error flag being deactivated.
-
Patent Agency Ranking
公开(公告)号：US11463110B2
公开(公告)日：2022-10-04
申请号：US16987554
申请日：2020-08-07
Applicant: Samsung Electronics Co., Ltd.
Inventor： Sungrae Kim , Kijun Lee , Myungkyu Lee , Sunghye Cho , Chanki Kim , Yeonggeol Song
Abstract: A memory controller includes an error correction circuit and a central processing unit (CPU) to control the error correction circuit. The error correction circuit includes an error correction code (ECC) decoder and a memory to store a parity check matrix. The ECC decoder performs an ECC decoding on a codeword read from the memory module to: (i) generate a first syndrome and a second syndrome, (ii) generate a decoding mode flag associated with a type of errors in the codeword based on the second syndrome and a decision syndrome, (iii) operate in one of a first decoding mode and a second decoding mode based on the decoding mode flag, and (iv) selectively correct one of a chip error associated with one of the data chips and one or more symbol errors in the codeword.
-
公开(公告)号：US12236991B1
公开(公告)日：2025-02-25
申请号：US18188256
申请日：2023-03-22
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Eunae Lee , Sunghye Cho , Kijun Lee , Junjin Kong , Yeonggeol Song
IPC: G11C11/406 , G06F12/06 , G11C11/408
Abstract: A memory device includes a memory cell array, an address manager and a refresh controller. The memory cell array includes a plurality of memory cells coupled to a plurality of word-lines. The address manager samples access addresses provided from a memory controller to generate sampling addresses and determines a capture address from among the access addresses, based on a time interval between refresh commands from the memory controller. The refresh controller refreshes target memory cells from among the plurality of memory cells based on one of a maximum access address from among the sampling address and the captured address.
-
公开(公告)号：US20250036521A1
公开(公告)日：2025-01-30
申请号：US18770435
申请日：2024-07-11
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Myungkyu Lee , Seongmuk Kang , Jae-Gon Lee , Kyomin Sohn , Yeonggeol Song , Kijun Lee
IPC: G06F11/10
Abstract: An example CXL (Compute eXpress Link)-based memory module includes a memory device and a controller. The memory device includes a plurality of volatile memory cells and stores data or reads the stored data. The controller communicates with a host device through a CXL interface and controls the memory device. The controller includes an error correction code (ECC) circuit that generates a first codeword by adding a parity vector generated based on Reed-Solomon encoding to data received from the host device, an error injecting circuit that generates an error symbol and generates a second codeword by injecting the error symbol into at least a portion of the first codeword, and a memory device interface that controls the memory device such that the second codeword where the error symbol is injected is stored in the memory device. The controller determines a number of error symbols to be injected into the second codeword.
-
公开(公告)号：US11860734B2
公开(公告)日：2024-01-02
申请号：US17736154
申请日：2022-05-04
Applicant: Samsung Electronics Co., Ltd.
Inventor： Sungrae Kim , Sunghye Cho , Yeonggeol Song , Kijun Lee , Myungkyu Lee
CPC classification number: G06F11/1068 , G06F11/0772 , G06F11/1048 , H03M13/1108
Abstract: A semiconductor memory device includes a memory cell array, an on-die error correction code (ECC) engine, and a control logic circuit. The on-die ECC engine, based on an ECC, in a write operation, performs an ECC encoding on main data to generate first parity data, selectively replaces a portion of the first parity data with a poison flag to generate second parity data based on a poison mode signal, provides the main data to a normal cell region in a target page of the memory cell array, and provides the first parity data to a parity cell region in the target page or provides the poison flag and the second parity data to the parity cell region. The control logic circuit controls the on-die ECC engine and generates the poison mode signal, based on a command and an address from a memory controller.
-
公开(公告)号：US11829614B2
公开(公告)日：2023-11-28
申请号：US17842981
申请日：2022-06-17
Applicant: Samsung Electronics Co., Ltd.
Inventor： Yeonggeol Song , Sungrae Kim , Kijun Lee , Myungkyu Lee , Eunae Lee , Sunghye Cho
CPC classification number: G06F3/0626 , G06F3/064 , G06F3/0679 , G06F11/1068
Abstract: A semiconductor memory device includes a buffer die and a plurality of memory dies. An error correction code (ECC) engine in one of the memory dies performs an RS encoding on a main data to generate a parity data and performs a RS decoding, using a parity check matrix, on the main data and the parity data. The parity check matrix includes sub matrixes and each of the sub matrixes corresponds to two different symbols. Each of the sub matrixes includes two identity sub matrixes and two same alpha matrixes, the two identity sub matrixes are disposed in a first diagonal direction of the sub matrix and the two same alpha matrixes are disposed in a second diagonal direction. A number of high-level value elements in a y-th row of the parity check matrix is the same as a number of high-level value elements in a (y+p)-th row.
-
-
-
-
-
-
-
-
-
Search Results
23
records
(took 0.021 seconds)
