公开(公告)号：US20190130950A1

公开(公告)日：2019-05-02

申请号：US15985200

申请日：2018-05-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： Young-Hun Kim ,  Sihong Kim

IPC: G11C7/10 ,  G11C7/22 ,  G11C11/4093 ,  G11C11/4091

CPC classification number: G11C11/4093 ,  G11C5/025 ,  G11C7/106 ,  G11C7/1066 ,  G11C7/1087 ,  G11C7/1093 ,  G11C7/222 ,  G11C11/4076 ,  G11C11/4091 ,  G11C29/028 ,  G11C2207/105 ,  G11C2207/107 ,  G11C2207/2254

Abstract: A semiconductor memory device includes a memory core that performs reading and writing of data, data delivery and training blocks that are connected between first pads and the memory core, and at least one data delivery, clock generation and training block that is connected between at least one second pad and the memory core. In a first training operation, the data delivery and training blocks output first training data, received through the first pads, through the first pads as second training data. In a second training operation, at least one of the data delivery and training blocks outputs third training data, received through the at least one second pad, through at least one of the first pads as fourth training data. The second training data and the fourth training data are output in synchronization with read data strobe signals output through the at least one second pad.

公开(公告)号：US09672894B2

公开(公告)日：2017-06-06

申请号：US14197437

申请日：2014-03-05

Applicant: Samsung Electronics Co., Ltd.

Inventor： Young-Hun Kim ,  In-Chul Jeong

IPC: G11C11/406 ,  G11C11/408 ,  G11C11/401 ,  G11C7/10

CPC classification number: G11C11/408 ,  G11C7/1063 ,  G11C11/40611

Abstract: A method of controlling a refresh operation for a memory device is disclosed. The method includes storing a first row address corresponding to a first row of a memory cell array, storing one or more second row addresses corresponding to one or more second rows of the memory cell array, the one or more second row addresses corresponding to the first row address, sequentially generating row addresses as a refresh row address during a first refresh interval, for each generated row address, when a generated row address identical to one of the one or more second row addresses is detected, stopping the generation of row addresses and sequentially outputting the one second row address and the first row address as the refresh row address, restarting the generation of the row addresses as the refresh row address after outputting the one second row address and the first row address.

公开(公告)号：US09076669B2

公开(公告)日：2015-07-07

申请号：US13833153

申请日：2013-03-15

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ju Youn Kim ,  Young-Hun Kim

IPC: H01L21/70 ,  H01L27/088 ,  H01L21/02 ,  H01L27/11 ,  H01L21/8238 ,  H01L27/092 ,  H01L21/28 ,  H01L29/51 ,  H01L29/78

CPC classification number: H01L29/517 ,  H01L21/02 ,  H01L21/28088 ,  H01L21/28167 ,  H01L21/28194 ,  H01L21/823857 ,  H01L27/088 ,  H01L27/092 ,  H01L27/1104 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/78

Abstract: A semiconductor device having high-k gate insulation films and a method of fabricating the semiconductor device are provided. The semiconductor device includes a first gate insulation film on a substrate and the first gate insulation film includes a material selected from the group consisting of HfO2, ZrO2, Ta2O5, TiO2, SrTiO3 and (Ba,Sr)TiO3, and lanthanum (La). Additionally, the semiconductor device includes a first barrier film on the first gate insulation film, a first gate electrode on the first barrier film, and n-type source/drain regions in the substrate at both sides of the first gate electrode.

Abstract translation: 提供了具有高k栅极绝缘膜的半导体器件和制造半导体器件的方法。 半导体器件包括在衬底上的第一栅极绝缘膜，第一栅极绝缘膜包括选自HfO 2，ZrO 2，Ta 2 O 5，TiO 2，SrTiO 3和（Ba，Sr）TiO 3和镧（La）的材料。 此外，半导体器件包括第一栅极绝缘膜上的第一阻挡膜，第一阻挡膜上的第一栅极电极和第一栅电极两侧的基板中的n型源极/漏极区域。

公开(公告)号：US20130272082A1

公开(公告)日：2013-10-17

申请号：US13770538

申请日：2013-02-19

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Young-Hun Kim ,  Inchul Jeong

IPC: G11C11/402 ,  G11C7/12

CPC classification number: G11C11/402 ,  G11C7/12 ,  G11C11/40615 ,  G11C11/40618

Abstract: A refresh circuit in a semiconductor memory device performs a multi-enable skew refresh operation during each periodic refresh operation. The refresh circuit includes a signal generation unit configured to generate a plurality of refresh signals having different timings during a refresh operation period, a first refresh circuit configured to enable refresh target lines associated with a first memory group in a memory cell array through operation periods of at least two time periods by using some of the refresh signals, and a second refresh circuit configured to enable refresh target lines associated with a second memory group differing from the first memory group through operation periods of at least two time periods by using some or all of the rest of the refresh signals. Enable timings of the first and second refresh circuits do not coincide each other.

Abstract translation: 半导体存储器件中的刷新电路在每个周期性刷新操作期间执行多使能偏斜刷新操作。 刷新电路包括：信号生成单元，被配置为在刷新操作期间生成具有不同定时的多个刷新信号;第一刷新电路，被配置为使存储单元阵列中与第一存储器组相关联的刷新目标线通过操作周期 通过使用一些刷新信号的至少两个时间段，以及第二刷新电路，被配置为通过使用一些或全部的操作来使能与第一存储器组不同的第二存储器组的刷新目标线通过至少两个时间段的操作周期 剩下的刷新信号。 启用第一和第二刷新电路的定时不一致。

公开(公告)号：US10347323B2

公开(公告)日：2019-07-09

申请号：US15985200

申请日：2018-05-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： Young-Hun Kim ,  Sihong Kim

IPC: G11C11/40 ,  G11C11/4093 ,  G11C7/10 ,  G11C11/4091 ,  G11C7/22

Abstract: A semiconductor memory device includes a memory core that performs reading and writing of data, data delivery and training blocks that are connected between first pads and the memory core, and at least one data delivery, clock generation and training block that is connected between at least one second pad and the memory core. In a first training operation, the data delivery and training blocks output first training data, received through the first pads, through the first pads as second training data. In a second training operation, at least one of the data delivery and training blocks outputs third training data, received through the at least one second pad, through at least one of the first pads as fourth training data. The second training data and the fourth training data are output in synchronization with read data strobe signals output through the at least one second pad.

公开(公告)号：US08908461B2

公开(公告)日：2014-12-09

申请号：US13770538

申请日：2013-02-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： Young-Hun Kim ,  Inchul Jeong

IPC: G11C7/00 ,  G11C7/12 ,  G11C11/406 ,  G11C11/402

CPC classification number: G11C11/402 ,  G11C7/12 ,  G11C11/40615 ,  G11C11/40618

Abstract: A refresh circuit in a semiconductor memory device performs a multi-enable skew refresh operation during each periodic refresh operation. The refresh circuit includes a signal generation unit configured to generate a plurality of refresh signals having different timings during a refresh operation period, a first refresh circuit configured to enable refresh target lines associated with a first memory group in a memory cell array through operation periods of at least two time periods by using some of the refresh signals, and a second refresh circuit configured to enable refresh target lines associated with a second memory group differing from the first memory group through operation periods of at least two time periods by using some or all of the rest of the refresh signals. Enable timings of the first and second refresh circuits do not coincide each other.

Abstract translation: 半导体存储器件中的刷新电路在每个周期性刷新操作期间执行多使能偏斜刷新操作。 刷新电路包括：信号生成单元，被配置为在刷新操作期间生成具有不同定时的多个刷新信号;第一刷新电路，被配置为使存储单元阵列中与第一存储器组相关联的刷新目标线通过操作周期 通过使用一些刷新信号的至少两个时间段，以及第二刷新电路，被配置为通过使用一些或全部的操作来使能与第一存储器组不同的第二存储器组的刷新目标行通过至少两个时间段的操作周期 剩下的刷新信号。 启用第一和第二刷新电路的定时不一致。

公开(公告)号：US12068326B2

公开(公告)日：2024-08-20

申请号：US18176463

申请日：2023-02-28

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Young-Hun Kim ,  Jae-Seok Yang ,  Hae-Wang Lee

IPC: H01L27/118 ,  H01L21/8238 ,  H01L27/02

CPC classification number: H01L27/11807 ,  H01L21/823814 ,  H01L21/823878 ,  H01L27/0207 ,  H01L2027/11829 ,  H01L2027/11861 ,  H01L2027/11864 ,  H01L2027/11881

Abstract: A semiconductor device includes a substrate having cell areas and power areas that are alternately arranged in a second direction. Gate structures extend in the second direction. The gate structures are spaced apart from each other in a first direction perpendicular to the second direction. Junction layers are arranged at both sides of each gate structure. The junction layers are arranged in the second direction such that each of the junction layer has a flat portion that is proximate to the power area. Cutting patterns are arranged in the power areas. The cutting patterns extend in the first direction such that each of the gate structures and each of the junction layers in neighboring cell areas are separated from each other by the cutting pattern.

公开(公告)号：USRE49467E1

公开(公告)日：2023-03-21

申请号：US17131149

申请日：2020-12-22

Applicant: Samsung Electronics Co., Ltd.

Inventor： Young-Hun Kim ,  Sihong Kim

IPC: G11C11/40 ,  G11C11/4093 ,  G11C7/10 ,  G11C11/4091 ,  G11C7/22 ,  G11C5/02 ,  G11C29/02 ,  G11C11/4076

Abstract: A semiconductor memory device includes a memory core that performs reading and writing of data, data delivery and training blocks that are connected between first pads and the memory core, and at least one data delivery, clock generation and training block that is connected between at least one second pad and the memory core. In a first training operation, the data delivery and training blocks output first training data, received through the first pads, through the first pads as second training data. In a second training operation, at least one of the data delivery and training blocks outputs third training data, received through the at least one second pad, through at least one of the first pads as fourth training data. The second training data and the fourth training data are output in synchronization with read data strobe signals output through the at least one second pad.

公开(公告)号：US11600639B2

公开(公告)日：2023-03-07

申请号：US17087321

申请日：2020-11-02

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Young-Hun Kim ,  Jae-Seok Yang ,  Hae-Wang Lee

IPC: H01L27/118 ,  H01L21/8238 ,  H01L27/02

Abstract: A semiconductor device includes a substrate having cell areas and power areas that are alternately arranged in a second direction. Gate structures extend in the second direction. The gate structures are spaced apart from each other in a first direction perpendicular to the second direction. Junction layers are arranged at both sides of each gate structure. The junction layers are arranged in the second direction such that each of the junction layer has a flat portion that is proximate to the power area. Cutting patterns are arranged in the power areas. The cutting patterns extend in the first direction such that each of the gate structures and each of the junction layers in neighboring cell areas are separated from each other by the cutting pattern.

公开(公告)号：US10728658B2

公开(公告)日：2020-07-28

申请号：US15983460

申请日：2018-05-18

Applicant: Samsung Electronics Co., Ltd.

Inventor： Myung-Jin Lee ,  Young-Hun Kim

IPC: H04R3/00 ,  H02H1/00 ,  H02H7/20 ,  H01R13/703 ,  H02H9/04

Abstract: An electronic circuit includes an output generator and an over-voltage detector. The output generator is configured to output an output signal to an output terminal. In response to an amplitude of a voltage of the output terminal being greater than an allowable amplitude, the over-voltage detector is configured to output an over-voltage detection signal of a first logic value, such that elements included in the output generator are turned off. In response to the over-voltage detector outputting the over-voltage detection signal of the first logic value again before a reference time elapses after the first logic value of the over-voltage detection signal changes to a second logic value of the over-voltage detection signal, the turned-off elements remain turned off. In response to the over-voltage detector outputting the over-voltage detection signal of the second logic value during the reference time, the turned-off elements are turned on.