公开(公告)号：US11482263B2

公开(公告)日：2022-10-25

申请号：US17239647

申请日：2021-04-25

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sehwan Park ,  Jinyoung Kim ,  Youngdeok Seo ,  Ilhan Park

IPC: G11C7/10 ,  G11C7/14 ,  G11C7/18 ,  G11C8/08

Abstract: A storage device includes at least one non-volatile memory device and a controller configured to control the at least one non-volatile memory device. The at least one non-volatile memory device performs an on-chip valley search (OVS) operation by latching a read command at an edge of a write enable (WE) signal according to a command latch enable (CLE) signal and an address latch enable (ALE) signal. The controller receives detection information according to the OVS operation from the at least one non-volatile memory device in response to a specific command. The OVS operation includes a first OVS operation using a read level and a second OVS operation using a changed read level.

公开(公告)号：US20220139484A1

公开(公告)日：2022-05-05

申请号：US17353583

申请日：2021-06-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jinyoung Kim ,  Sehwan Park ,  Youngdeok Seo ,  Ilhan Park

IPC: G11C29/42 ,  G11C29/44 ,  G11C16/34 ,  G11C16/04 ,  G11C16/26 ,  G11C16/08 ,  G11C16/24

Abstract: A nonvolatile memory device includes a plurality of memory blocks and a control logic circuit configured to perform a first page on-chip valley search (OVS) operation on memory cells connected to one wordline of a memory block selected in response to an address, among the plurality of memory blocks, in response to a first read command. The control logic circuit is further configured to change a read level of at least one state using detection information of the first page OVS operation, and to perform a second page read operation on the memory cells using the changed read level in response to a second read command.

公开(公告)号：US12300335B2

公开(公告)日：2025-05-13

申请号：US17893476

申请日：2022-08-23

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hyuna Kim ,  Woohyun Kang ,  Youngdeok Seo ,  Hyunkyo Oh ,  Donghoo Lim

IPC: G11C16/34 ,  G11C16/26

Abstract: Disclosed is a storage controller which includes a history table and communicates with a non-volatile memory device. A method of operating the storage controller includes determining whether history data of a target memory block are registered at the history table, providing a history read request for the target memory block based on the history data when it is determined that the history data are registered, receiving first raw data corresponding to the history read request from the non-volatile memory device, generating skew information of the target memory block based on the first raw data and the history data, and determining whether to perform a read reclaim operation of the target memory block, based on the skew information.

公开(公告)号：US12300325B2

公开(公告)日：2025-05-13

申请号：US18170893

申请日：2023-02-17

Applicant: Samsung Electronics Co., Ltd.

Inventor： Woohyun Kang ,  Jin-Young Kim ,  Hyuna Kim ,  Se Hwan Park ,  Youngdeok Seo ,  Hyunkyo Oh ,  Heewon Lee ,  Donghoo Lim

IPC: G11C16/12 ,  G06F11/10 ,  G11C16/26

Abstract: A method of operating a non-volatile memory device, which is configured to communicate with a storage controller includes: receiving a first request indicating a read reclaim determination and including environment information from the storage controller, performing a first on-chip read operation for generating first distribution information based on the first request, determining whether a read reclaim is required based on the first distribution information, and providing the storage controller with a determination result having a first bit value in response to determining that the read reclaim is required.

公开(公告)号：US11862273B2

公开(公告)日：2024-01-02

申请号：US18068337

申请日：2022-12-19

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sehwan Park ,  Jinyoung Kim ,  Youngdeok Seo ,  Dongmin Shin ,  Joonsuc Jang ,  Sungmin Joe

IPC: G11C29/42 ,  G11C29/44 ,  G11C29/18 ,  G11C16/10 ,  G11C29/12 ,  G11C16/26

CPC classification number: G11C29/42 ,  G11C16/102 ,  G11C16/26 ,  G11C29/12015 ,  G11C29/18 ,  G11C29/4401 ,  G11C2029/1202 ,  G11C2029/1204 ,  G11C2029/1802

Abstract: A storage device includes a nonvolatile memory device and a memory controller to control the nonvolatile memory device. The nonvolatile memory device includes a memory cell array. The memory cell array includes a normal cell region, a parity cell region and a redundancy cell region. First bit-lines are connected to the normal cell region and the parity cell region and second bit-lines are connected to the redundancy cell region. The memory controller includes an error correction code (ECC) engine to generate parity data. The memory controller stores user data in the normal cell region, controls the nonvolatile memory device to perform a column repair on first defective bit-lines among the first bit-lines, assigns additional column addresses to the first defective bit-lines and the second bit-lines and stores at least a portion of the parity data in a region corresponding to the additionally assigned column addresses.

公开(公告)号：US11817153B2

公开(公告)日：2023-11-14

申请号：US17503197

申请日：2021-10-15

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jinyoung Kim ,  Sehwan Park ,  Ilhan Park ,  Youngdeok Seo ,  Dongmin Shin

IPC: G11C16/16 ,  G11C16/08 ,  G11C16/04 ,  G11C16/26 ,  G11C16/24

CPC classification number: G11C16/16 ,  G11C16/0433 ,  G11C16/08 ,  G11C16/24 ,  G11C16/26

Abstract: A memory device may include a memory block and a control circuit. The memory block may include a first sub-block and a second sub-block that are connected between a common source line and a plurality of bit lines and may be vertically stacked. The control circuit may be configured to select any one of the common source line and the plurality of bit lines as a transmission path of an erase voltage based on positions of the first sub-block and the second sub-block, and perform erase operations on the first sub-block and the second sub-block in units of sub-blocks.

公开(公告)号：US11670387B2

公开(公告)日：2023-06-06

申请号：US17328487

申请日：2021-05-24

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Youngdeok Seo ,  Jinyoung Kim ,  Sehwan Park ,  Dongmin Shin

IPC: G11C16/34 ,  G11C16/26 ,  G06N20/10 ,  G11C16/08 ,  G11C16/10 ,  G06F18/214

CPC classification number: G11C16/3481 ,  G06F18/214 ,  G06N20/10 ,  G11C16/08 ,  G11C16/102 ,  G11C16/26 ,  G11C16/3404

Abstract: A non-volatile memory device includes a memory cell array including memory cells, a page buffer circuit including page buffers respectively connected to bit lines, a buffer memory, and a control logic configured to control a read operation on the memory cells. In the read operation, the control logic obtains valley search detection information including read target block information and word line information by performing a valley search sensing operation on a distribution of threshold voltages of the memory cells, obtains a plurality of read levels using a read information model by inputting the valley search detection information into the read information model, and performs a main sensing operation for the read operation.

公开(公告)号：US20220254419A1

公开(公告)日：2022-08-11

申请号：US17450871

申请日：2021-10-14

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jinyoung Kim ,  Sehwan Park ,  Youngdeok Seo ,  Dongmin Shin

IPC: G11C16/30 ,  H01L25/065 ,  H01L25/18 ,  H01L23/00

Abstract: A memory system includes a non-volatile memory device including a machine learning (ML) module and a peripheral power management integrated circuit (IC), and a memory controller configured to command the non-volatile memory device to enter an idle mode by providing an external power command to the non-volatile memory device. The machine learning (ML) module configures a neural network and trains the neural network via machine learning, and the peripheral power management IC is configured to generate an internal power command that is different from the external power command based on the external power command and monitoring information corresponding to the ML module.

公开(公告)号：US20220214826A1

公开(公告)日：2022-07-07

申请号：US17376437

申请日：2021-07-15

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Youngdeok Seo ,  Jinyoung Kim ,  Sehwan Park ,  Dongmin Shin ,  Woohyun Kang ,  Shinho Oh

IPC: G06F3/06 ,  G06N3/08

Abstract: A method of operating a nonvolatile memory device is provided. The method includes: dividing a memory block of a plurality of memory blocks provided in the nonvolatile memory device into a plurality of retention groups; generating time-difference information including a plurality of erase program interval (EPI) values corresponding to the plurality of retention groups; generating offset information including a plurality of offset values corresponding to differences between a plurality of default read voltages and a plurality of corrected read voltages; generating compensated read voltages corresponding to a read address based on the offset information and the time-difference information; and performing a read operation to read data from the nonvolatile memory device based on the read address and the compensated read voltages.

公开(公告)号：US20250094062A1

公开(公告)日：2025-03-20

申请号：US18968373

申请日：2024-12-04

Applicant: Samsung Electronics Co., Ltd.

Inventor： Woohyun Kang ,  Su Chang Jeon ,  Suhyun Kim ,  Hyuna Kim ,  Youngdeok Seo ,  Hyunkyo Oh ,  Donghoo Lim ,  Byungkwan Chun

IPC: G06F3/06

Abstract: Disclosed is a method of operating a storage controller which communicates with a non-volatile memory device. The method includes providing a read command to the non-volatile memory device, receiving first read data and first distribution information corresponding to the read command from the non-volatile memory device, determining whether an error of the first read data is uncorrectable, and updating offset information of a history table in the storage controller based on the first distribution information, in response to determining that the error of the first read data is correctable.