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公开(公告)号:US20180026077A1
公开(公告)日:2018-01-25
申请号:US15421498
申请日:2017-02-01
Applicant: Samsung Electronics Co., Ltd.
Inventor: Zhe Wu , Dong-ho Ahn , Hideki Horii , Soon-oh Park , Jeong-hee Park , Jin-woo Lee , Dong-jun Seong , Seol Choi
CPC classification number: H01L27/2481 , H01L45/06 , H01L45/1233 , H01L45/126 , H01L45/143 , H01L45/144 , H01L45/1675
Abstract: A memory device includes a variable resistance layer and a selection device layer electrically connected to the variable resistance layer. The memory device further included a chalcogenide switching material that reduces leakage current and has, for example, a composition according to chemical formula 1 below, [GeXSiY(AsaTe1-a)Z](1-U)[N]U (1) (where 0.05≦X≦0.1, 0.15≦Y≦0.25, 0.7≦Z≦0.8, X+Y+Z=1, 0.45≦a≦0.6, and 0.08≦U≦0.2).
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公开(公告)号:US20210193922A1
公开(公告)日:2021-06-24
申请号:US16988957
申请日:2020-08-10
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor: Ja Bin Lee , Zhe Wu , Kwangmin Park , Gwangguk An , Dongho Ahn , Seung-Geun Yu , Jinwoo Lee
Abstract: A variable resistance memory device includes a plurality of memory cells arranged on a substrate. Each of the memory cells includes a selection element pattern and a variable resistance pattern stacked on the substrate. The selection element pattern includes a first selection element pattern having a chalcogenide material and a second selection element pattern having a metal oxide and coupled to the first selection element pattern.
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公开(公告)号:US10546894B2
公开(公告)日:2020-01-28
申请号:US16226855
申请日:2018-12-20
Applicant: Samsung Electronics Co., Ltd.
Inventor: Zhe Wu , Dong-ho Ahn , Hideki Horii , Soon-oh Park , Jeong-hee Park , Jin-woo Lee , Dong-jun Seong , Seol Choi
Abstract: A memory device includes a plurality of word lines extending along a first direction and spaced apart from each other along a second direction that is perpendicular to the first direction; a plurality of bit lines extending along the second direction and spaced apart from each other in the first direction, the plurality of bit lines being spaced apart from the plurality of word lines in a third direction that is perpendicular to both the first and second directions; and a plurality of memory cells being respectively arranged between the corresponding word and bit lines. Each of the memory cells includes a selection device layer, and a variable resistance layer, wherein the selection device layer includes a chalcogenide switching material having a composition according to a particular chemical formula.
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公开(公告)号:US11581367B2
公开(公告)日:2023-02-14
申请号:US17209660
申请日:2021-03-23
Applicant: Samsung Electronics Co., Ltd.
Inventor: Dongho Ahn , Segab Kwon , Chungman Kim , Kwangmin Park , Zhe Wu , Seunggeun Yu , Wonjun Lee , Jabin Lee , Jinwoo Lee
Abstract: A semiconductor device includes a semiconductor substrate, a peripheral device on the semiconductor substrate, a lower insulating structure on the semiconductor substrate and covering the peripheral device, a first conductive line on the lower insulating structure, a memory cell structure on the first conductive line, and a second conductive line on the memory cell structure. The memory cell structure may include an information storage material pattern and a selector material pattern on the lower insulating structure in a vertical direction. The selector material pattern may include a first selector material layer including a first material and a second selector material layer including a second material. The second selector material layer may have a threshold voltage drift higher than that of the first material. The second selector material layer may have a second width narrower than a first width of the first selector material layer.
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公开(公告)号:US11205682B2
公开(公告)日:2021-12-21
申请号:US16446812
申请日:2019-06-20
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor: Zhe Wu , Ja-bin Lee , Jin-woo Lee , Kyu-bong Jung
Abstract: A memory device includes first conductive lines extending in a first direction, second conductive lines extending in a second direction, and a plurality of memory cells each arranged between the first and second conductive lines and each including a variable resistance memory layer and a switch material pattern. The switch material pattern includes an element injection area arranged in an outer area of the switch material pattern, and an internal area covered by the element injection area. The internal area contains a first content of at least one element from arsenic (As), sulfur (S), selenium (Se), and tellurium (Te), the element injection area contains a second content of the at least one element from As, S, Se, and Te, and the second content has a profile in which a content of the at least one element decreases away from the at least one surface of the switch material pattern.
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公开(公告)号:US20190148456A1
公开(公告)日:2019-05-16
申请号:US16226855
申请日:2018-12-20
Applicant: Samsung Electronics Co., Ltd.
Inventor: Zhe Wu , Dong-ho Ahn , Hideki Horii , Soon-oh Park , Jeong-hee Park , Jin-woo Lee , Dong-jun Seong , Seol Choi
CPC classification number: H01L27/2481 , H01L45/06 , H01L45/1233 , H01L45/126 , H01L45/143 , H01L45/144 , H01L45/1675
Abstract: A memory device includes a plurality of word lines extending along a first direction and spaced apart from each other along a second direction that is perpendicular to the first direction; a plurality of bit lines extending along the second direction and spaced apart from each other in the first direction, the plurality of bit lines being spaced apart from the plurality of word lines in a third direction that is perpendicular to both the first and second directions; and a plurality of memory cells being respectively arranged between the corresponding word and bit lines. Each of the memory cells includes a selection device layer, and a variable resistance layer, wherein the selection device layer includes a chalcogenide switching material having a composition according to a particular chemical formula.
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公开(公告)号:US20180277601A1
公开(公告)日:2018-09-27
申请号:US15832958
申请日:2017-12-06
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor: Dong-ho Ahn , Zhe Wu , Soon-oh Park , Hideki Horii
CPC classification number: H01L27/2427 , H01L27/224 , H01L27/2436 , H01L27/2463 , H01L27/2481 , H01L45/04 , H01L45/06 , H01L45/065 , H01L45/1233 , H01L45/1246 , H01L45/126 , H01L45/141 , H01L45/143 , H01L45/144 , H01L45/146 , H01L45/1683
Abstract: A memory device is provided. The memory device includes a variable resistance layer. A selection device layer is electrically connected to the variable resistance layer. The selection device layer includes a chalcogenide switching material having a composition according to chemical formula 1 below, [GeASeBTeC](1-U)[X]U (1) where 0.20≤A≤0.40, 0.40≤B≤0.70, 0.05≤C≤0.25, A+B+C=1, 0.0≤U≤0.20, and X is at least one selected from boron (B), carbon (C), nitrogen (N), oxygen (O), phosphorus (P), or sulfur (S).
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公开(公告)号:US09985204B2
公开(公告)日:2018-05-29
申请号:US15451961
申请日:2017-03-07
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor: Jinwoo Lee , Jeonghee Park , Dongho Ahn , Zhe Wu , Heeju Shin , Ja bin Lee
CPC classification number: H01L45/141 , H01L43/08 , H01L43/10 , H01L45/06 , H01L45/1233 , H01L45/1253 , H01L45/145 , H01L45/16
Abstract: A semiconductor memory device including first lines and second lines overlapping and intersecting each other, variable resistance memory elements disposed at intersections between the first lines and the second lines, and switching elements disposed between the variable resistance memory elements and the first lines. At least one of the switching elements includes first and second chalcogenide compound layers, and conductive nano-dots disposed between the first and second chalcogenide compound layers.
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公开(公告)号:US09318700B2
公开(公告)日:2016-04-19
申请号:US14740929
申请日:2015-06-16
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor: Zhe Wu , Jeong-Hee Park , Dong-Ho Ahn , Jung-Hwan Park , Jun-Ku Ahn , Sung-Lae Cho , Hideki Horii
CPC classification number: H01L45/06 , H01L27/2409 , H01L27/2463 , H01L45/1233 , H01L45/1253 , H01L45/141 , H01L45/144 , H01L45/1616 , H01L45/1625 , H01L45/1641 , H01L45/1666 , H01L45/1683
Abstract: In a method of manufacturing a phase change memory device, an insulating interlayer having a through opening is formed on a substrate, at least one conformal phase change material layer pattern is formed along the sides of the opening, and a plug-like phase change material pattern having a composition different from that of each conformal phase change material layer pattern is formed on the at least one conformal phase change material layer pattern as occupying a remaining portion of the opening. Energy is applied to the phase change material layer patterns to form a mixed phase change material layer pattern including elements from the conformal and plug-like phase change material layer patterns.
Abstract translation: 在相变存储装置的制造方法中,在基板上形成具有通孔的绝缘中间层,沿开口侧形成至少一个共形相变材料层图案,并且形成插塞状相变材料 具有不同于每个共形相变材料层图案的组成的图案形成在占据开口的剩余部分的至少一个共形相变材料层图案上。 将能量施加到相变材料层图案以形成包括来自保形和插塞状相变材料层图案的元件的混合相变材料层图案。
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公开(公告)号:US11616197B2
公开(公告)日:2023-03-28
申请号:US16988957
申请日:2020-08-10
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor: Ja Bin Lee , Zhe Wu , Kwangmin Park , Gwangguk An , Dongho Ahn , Seung-Geun Yu , Jinwoo Lee
Abstract: A variable resistance memory device includes a plurality of memory cells arranged on a substrate. Each of the memory cells includes a selection element pattern and a variable resistance pattern stacked on the substrate. The selection element pattern includes a first selection element pattern having a chalcogenide material and a second selection element pattern having a metal oxide and coupled to the first selection element pattern.
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