公开(公告)号：US20150149725A1

公开(公告)日：2015-05-28

申请号：US14088446

申请日：2013-11-25

申请人： Ashish Mathur ,  Sandeep Jain

发明人： Ashish Mathur ,  Sandeep Jain

IPC分类号： G06F12/08

CPC分类号： G06F9/3004 ,  G06F8/45 ,  G06F8/52 ,  G06F9/45558

摘要： A multi-threaded binary translation system performs atomic operations by a thread, such operations include processing a load linked instruction and a store conditional instruction. The store conditional instruction updates data stored in a shared memory address only when at least three conditions are satisfied. The conditions are: a copy of a load linked shared memory address of the load linked instruction is the same as the store conditional shared memory address, a reservation flag indicates that the thread has a valid reservation, and the copy of data stored by the load linked instruction is the same as data stored in the store conditional shared memory address.

摘要翻译： 多线程二进制翻译系统通过线程执行原子操作，这样的操作包括处理加载链接指令和存储条件指令。 存储条件指令仅在满足至少三个条件时更新存储在共享存储器地址中的数据。 条件是：负载链接指令的负载链接共享存储器地址的副本与存储条件共享存储器地址相同，保留标志指示线程具有有效预留，以及负载存储的数据副本 链接指令与存储在存储条件共享存储器地址中的数据相同。

公开(公告)号：US20150121127A1

公开(公告)日：2015-04-30

申请号：US14067920

申请日：2013-10-30

申请人： Sandeep Jain

发明人： Sandeep Jain

IPC分类号： G06F11/14

CPC分类号： G06F11/1402 ,  G06F11/3636 ,  G06F12/0802 ,  G06F12/0875

摘要： A functional simulator with watchpoint support includes a CPU having a first-level DMI cache, a watchpoint manager having a second-level DMI cache, an interconnect module, and a memory controller. The simulator is operated by a front-end tool. Watchpoints corresponding to a predetermined memory addresses are set by the front-end tool and stored as a watchpoint address list in the watchpoint manager. When a memory access request is received by the first-level DMI cache, after a failure to complete the memory access request, the CPU transmits the request to the watchpoint manager. The watchpoint manager searches for a memory address associated with the memory access request in the watchpoint address list. If a match is found, the watchpoint manager generates a watchpoint hit signal and notifies the front-end tool.

摘要翻译： 具有观察点支持的功能模拟器包括具有第一级DMI缓存的CPU，具有二级DMI高速缓存的观察点管理器，互连模块和存储器控制器。 模拟器由前端工具操作。 与预定存储器地址相对应的观察点由前端工具设置，并作为观察点地址列表存储在观察点管理器中。 当第一级DMI缓存接收到存储器访问请求时，在完成存储器访问请求失败之后，CPU将该请求发送给观察点管理器。 观察点管理器在观察点地址列表中搜索与存储器访问请求相关联的存储器地址。 如果找到匹配，则观察点管理器生成观察点命中信号并通知前端工具。

公开(公告)号：US07809827B1

公开(公告)日：2010-10-05

申请号：US11516878

申请日：2006-09-07

申请人： Manoj Apte ,  Sandeep Jain ,  Fritz Budiyanto ,  Senthil Kumar Duraiswamy ,  Saravanan Deenadayalan ,  Yulianto Kokasih Ko

发明人： Manoj Apte ,  Sandeep Jain ,  Fritz Budiyanto ,  Senthil Kumar Duraiswamy ,  Saravanan Deenadayalan ,  Yulianto Kokasih Ko

IPC分类号： G06F15/173

CPC分类号： H04L43/028 ,  H04L45/10 ,  H04L45/38

摘要： A network device comprises a service card (e.g., a lawful intercept (LI) service card) executing a communication protocol to receive, from one or more sources (e.g., law enforcement agents), intercept information specifying at least one destination and criteria for matching one or more packet flows. The network device further includes a network interface card to receive a packet from a network, and a control unit to provide the packet from the interface card to the LI service card. The LI service card executes a flow match detection module that, when the packet matches the criteria of the intercept information, forwards the packet to the destination specified by the intercept information. The network device may provide real-time intercept and relaying of specified network-based communications. Moreover, the techniques described herein allow LEAs to tap packet flows with little delay after specifying intercept information, e.g., within 50 milliseconds, even under high-volume networks.

摘要翻译： 网络设备包括执行通信协议的服务卡（例如合法拦截（LI）服务卡），以从一个或多个来源（例如执法人员）接收指定至少一个目的地的拦截信息和用于匹配的标准 一个或多个分组流。 网络设备还包括从网络接收分组的网络接口卡，以及将接口卡向L1服务卡提供分组的控制单元。 LI服务卡执行流匹配检测模块，当分组符合拦截信息的标准时，将分组转发到由拦截信息指定的目的地。 网络设备可以提供指定的基于网络的通信的实时拦截和中继。 此外，即使在高容量网络下，本文所描述的技术允许LEA在指定拦截信息（例如，在50毫秒内）之后稍微延迟地敲击分组流。

公开(公告)号：US07793037B2

公开(公告)日：2010-09-07

申请号：US11140772

申请日：2005-05-31

申请人： Sandeep Jain ,  Animesh Mishra ,  Jim Kardach

发明人： Sandeep Jain ,  Animesh Mishra ,  Jim Kardach

IPC分类号： G06F12/00

CPC分类号： G11C7/1021 ,  G11C7/1045 ,  G11C8/12

摘要： Systems and methods of managing memory provide for detecting a request to activate a memory portion that is limited in size to a partial page size, where the partial page size is less than a full page size associated with the memory. In one embodiment, detecting the request may include identifying a row address and partial page address associated with the request, where the partial page address indicates that the memory portion is to be limited to the partial page size.

摘要翻译： 管理存储器的系统和方法提供用于检测激活被限制为部分页面大小的部分页面大小的存储器部分的请求，其中部分页面大小小于与存储器相关联的整个页面大小。 在一个实施例中，检测请求可以包括识别与该请求相关联的行地址和部分页面地址，其中部分页面地址指示存储器部分被限制为部分页面大小。

公开(公告)号：US20100168849A1

公开(公告)日：2010-07-01

申请号：US12600967

申请日：2008-03-13

申请人： Dimitri Azar ,  Jose De La Cruz ,  Sandeep Jain

发明人： Dimitri Azar ,  Jose De La Cruz ,  Sandeep Jain

IPC分类号： A61F2/14

CPC分类号： A61F2/1651 ,  A61F2/14 ,  A61F2/142 ,  A61F2/15 ,  A61F2220/0008

摘要： The invention provides a transcorneal vision assistance device implantable in the eye of a patient. A preferred embodiment transcorneal microtelescope vision assistance device is implantable in the eye of a patient and includes a keratoprosthesis configured to replace a portion of the cornea of a patient and to secure the keratoprosthesis to a remaining front portion of the cornea. A microtelescope is carried by the keratoprosthesis for transcorneal mounting of the microtelescope.

摘要翻译： 本发明提供了一种可植入患者眼中的视神经视像辅助装置。 优选的实施方式，转角镜微视野镜视觉辅助装置可植入患者的眼睛中，并且包括构造成替换患者角膜的一部分并将角膜假体固定到角膜的剩余前部的角膜假体。 微型望远镜由角膜假体承载，用于微型望远镜的经角膜安装。

公开(公告)号：US07454639B2

公开(公告)日：2008-11-18

申请号：US11174060

申请日：2005-06-30

申请人： Sandeep Jain ,  James P. Kardach

发明人： Sandeep Jain ,  James P. Kardach

IPC分类号： G06F1/00 ,  G06F1/26 ,  G06F1/32

CPC分类号： G06F1/3275 ,  G06F1/3225 ,  Y02D10/14

摘要： A method, apparatus, and system are described in which a memory controller may have two or more registers to create and track zones of memory in a volatile memory device. The memory controller controls a power consumption state of a first zone of memory in the volatile memory device and a second zone of memory within the first volatile memory device on an individual basis; and one or more memory arrays contained within the first volatile memory device.

摘要翻译： 描述了一种方法，装置和系统，其中存储器控制器可以具有两个或更多个寄存器来创建和跟踪易失性存储器设备中的存储器区域。 存储器控制器在单独的基础上控制易失性存储器设备中的第一存储器区域和第一易失性存储器设备内的第二存储器区域的功耗状态; 以及包含在第一易失性存储器件内的一个或多个存储器阵列。

公开(公告)号：US07450456B2

公开(公告)日：2008-11-11

申请号：US11801909

申请日：2007-05-10

申请人： Sandeep Jain ,  David Wyatt ,  Jun Shi ,  Animesh Mishra ,  John Halbert ,  Melik Isbara

发明人： Sandeep Jain ,  David Wyatt ,  Jun Shi ,  Animesh Mishra ,  John Halbert ,  Melik Isbara

IPC分类号： G11C7/04 ,  G11C5/06

CPC分类号： G11C7/04 ,  G06F11/3037 ,  G06F11/3058 ,  G06F11/3089 ,  G11C5/04 ,  G11C5/143 ,  G11C7/1051 ,  G11C7/1063

摘要： The temperature for multiple devices of a memory module are determined. In one example a memory module includes a printed circuit board, a plurality of memory chips on the printed circuit board, each chip containing a plurality of memory cells and a thermal sensor, and a multiplexer on the printed circuit board, independent of the memory chips, coupled to each of the thermal sensors. A current source is coupled to the multiplexer to provide a current to each one of the thermal sensors, and a voltage detector is coupled to the multiplexer to detect a voltage from each of the thermal sensors when a current is applied. A temperature circuit is coupled to the voltage detector to determine a temperature for each memory chip based on the detected voltage.

摘要翻译： 确定存储器模块的多个设备的温度。 在一个示例中，存储器模块包括印刷电路板，印刷电路板上的多个存储器芯片，每个芯片包含多个存储单元和热传感器，以及印刷电路板上的多路复用器，独立于存储器芯片 ，耦合到每个热传感器。 电流源耦合到多路复用器以向每个热传感器提供电流，并且电压检测器耦合到多路复用器以在施加电流时检测来自每个热传感器的电压。 温度电路耦合到电压检测器，以基于检测到的电压来确定每个存储器芯片的温度。

公开(公告)号：US07185103B1

公开(公告)日：2007-02-27

申请号：US10241785

申请日：2002-09-10

申请人： Sandeep Jain

发明人： Sandeep Jain

IPC分类号： G06F15/16

CPC分类号： H04L43/026 ,  H04L43/18

摘要： Network analysis techniques are described for generating and outputting traffic flow packets which include traffic flow information indicative of network traffic flows. More specifically, the traffic flow packets may be generated and output in a rate-controlled fashion, which can avoid data loss of traffic flow information in the traffic flow packets. For example, rate-controlled transmission can be extremely useful in ensuring that transmitted traffic flow packets will be received by a packet flow collector without overloading input buffers of the packet flow collector.

摘要翻译： 描述了用于生成和输出包括指示网络业务流的业务流信息的业务流分组的网络分析技术。 更具体地，可以以速率控制的方式生成和输出业务流分组，这可以避免业​​务流分组中业务流信息的数据丢失。 例如，速率控制的传输在确保传输的业务流分组将被分组流收集器接收而不会使分组流收集器的输入缓冲器过载的情况下非常有用。

公开(公告)号：US20070006000A1

公开(公告)日：2007-01-04

申请号：US11174375

申请日：2005-06-30

申请人： Sandeep Jain ,  Paul Diefenbaugh ,  James Kardach ,  Ramkumar Vankatachary

发明人： Sandeep Jain ,  Paul Diefenbaugh ,  James Kardach ,  Ramkumar Vankatachary

IPC分类号： G06F1/00

CPC分类号： G06F1/3275 ,  G06F1/3228 ,  Y02D10/14

摘要： The methods for fine-grained power management of physical system memory allow portions of the system volatile memory to be independently power managed. The system volatile memory may be partitioned into a plurality of power management units (PMUs). Each PMU may have a pre-determined size or a variable size, which may be less than the size of a memory chip. Each PMU may be placed in a different memory state and independently power managed according to the memory state. At opportune times during the system active state, a fractional potion of the system volatile memory is shadowed into the system nonvolatile memory. Active data in the system volatile memory is rearranged prior to entering a power-saving mode and the PMUs containing the shadowed data may be powered off. Thus, power efficiency of the system volatile memory is improved.

摘要翻译： 用于物理系统存储器的细粒度电源管理的方法允许系统易失性存储器的一部分被独立地进行功率管理。 系统易失性存储器可以被划分成多个电源管理单元（PMU）。 每个PMU可以具有预定尺寸或可变尺寸，其可以小于存储器芯片的尺寸。 每个PMU可以被放置在不同的存储器状态，并且根据存储器状态独立地进行功率管理。 在系统活动状态期间的适时时刻，系统易失性存储器的分数部分被遮蔽到系统非易失性存储器中。 在进入省电模式之前，系统易失性存储器中的有效数据被重新排列，并且包含阴影数据的PMU可能被关闭。 因此，提高了系统易失性存储器的功率效率。

公开(公告)号：US20070005836A1

公开(公告)日：2007-01-04

申请号：US11148160

申请日：2005-06-07

申请人： Sandeep Jain ,  George Vergis ,  John Halbert ,  Nilesh Shah

发明人： Sandeep Jain ,  George Vergis ,  John Halbert ,  Nilesh Shah

IPC分类号： G06F13/38

CPC分类号： G06F13/4013 ,  G11C5/06 ,  G11C7/04 ,  G11C7/1006 ,  G11C8/20

摘要： Swizzle information for signal lines on a memory component may be stored on the memory component. The swizzle information may be transmitted to a memory controller which may include logic to receive the swizzle information which is then used to deswizzle data received from the memory component. Data may be transmitted from a memory device to a memory controller in a format that is tolerant of swizzling on signal lines between the device and the controller. The format may include codes having unique of numbers of values. Data may be sent in multi-code bursts that divide a data range into progressively smaller ranges. Other embodiments are described and claimed.

摘要翻译： 存储器组件上的信号线的交换信息可以存储在存储器组件上。 交换信息可以被发送到存储器控制器，存储器控制器可以包括用于接收转移信息的逻辑，然后用于去除从存储器组件接收的数据。 数据可以以容许在设备和控制器之间的信号线上进行转换的格式从存储器件发送到存储器控制器。 该格式可以包括具有唯一值的值的代码。 可以以将多个数字范围分割成逐渐变小的多码脉冲串来发送数据。 描述和要求保护其他实施例。