公开(公告)号：US6140671A

公开(公告)日：2000-10-31

申请号：US157401

申请日：1998-09-21

Applicant: Sang-in Lee

Inventor： Sang-in Lee

IPC: H01L27/04 ,  H01L21/02 ,  H01L21/285 ,  H01L21/822 ,  H01L21/8242 ,  H01L27/108 ,  H01L29/04 ,  H01L27/105 ,  H01L29/16 ,  H01L29/92

CPC classification number: H01L27/10852 ,  H01L28/55 ,  H01L28/60 ,  H01L21/28568 ,  Y10S148/148

Abstract: A capacitor in a semiconductor device having a dielectric film formed of high dielectric material and a manufacturing method therefor are provided. The capacitor consists of electrodes including a dielectric film and an amorphous SiC layer. Thus, the diffusion of oxygen atoms through a grain boundary into an underlayer and the formation of an oxide layer on the surface of the SiC layer can both be prevented, providing for a highly reliable capacitor electrode and an equivalent oxide thickness which is no thicker than required.

Abstract translation: 提供了具有由高介电材料形成的电介质膜的半导体器件中的电容器及其制造方法。 电容器由包括电介质膜和非晶SiC层的电极组成。 因此，可以防止氧原子通过晶界扩散到底层中，并且可以防止在SiC层的表面上形成氧化物层，从而提供高可靠性的电容器电极和等于不比厚度大的氧化物厚度 需要。

公开(公告)号：US6001660A

公开(公告)日：1999-12-14

申请号：US969672

申请日：1997-11-13

Applicant: Young-soh Park ,  Sang-in Lee ,  Cheol-seong Hwang ,  Doo-sup Hwang ,  Hag-Ju Cho

Inventor： Young-soh Park ,  Sang-in Lee ,  Cheol-seong Hwang ,  Doo-sup Hwang ,  Hag-Ju Cho

IPC: C23C14/14 ,  C23C14/58 ,  H01L21/02 ,  H01L21/28 ,  H01L21/768 ,  H01L21/822 ,  H01L21/8242 ,  H01L27/04 ,  H01L27/108 ,  H01G7/06

CPC classification number: H01L28/60 ,  H01L21/76882

Abstract: Methods of forming integrated circuit capacitors include the steps of forming an electrically insulating layer on a face of a semiconductor substrate and then patterning the electrically insulating layer to define a contact hole therein. A barrier metal layer is then formed in at least a portion of the contact hole. A lower electrode metal layer is then formed on the barrier metal layer and then planarized by reflowing the lower electrode metal layer at a temperature greater than about 650.degree. C. in a nitrogen gas ambient, to define a lower capacitor electrode. A layer of material having a high dielectric constant is then formed on the lower capacitor electrode. An upper capacitor electrode is then formed on the dielectric layer, opposite the lower capacitor electrode. The dielectric layer may comprise Ba(Sr, Ti)O.sub.3, Pb(Zr, Ti)O.sub.3, Ta.sub.2 O.sub.5, SiO.sub.2, SiN.sub.3, SrTiO.sub.3, PZT, SrBi.sub.2 Ta.sub.2 O.sub.9, (Pb, La)(Zr, Ti)O.sub.3 and Bi.sub.4 Ti.sub.3 O.sub.12. According to one embodiment of the present invention, the step of patterning the electrically insulating layer comprises patterning the electrically insulating layer to define a contact hole therein that exposes the face of the semiconductor substrate. The step of forming a barrier metal layer also preferably comprises depositing a conformal barrier metal layer on sidewalls of the contact hole and on the exposed face of the substrate. The barrier metal layer may be selected from the group consisting of TiN, CoSi, TaSiN, TiSiN, TaSi, TiSi, Ta and TaN.

Abstract translation: 形成集成电路电容器的方法包括以下步骤：在半导体衬底的表面上形成电绝缘层，然后对电绝缘层进行构图以在其中限定接触孔。 然后在接触孔的至少一部分中形成阻挡金属层。 然后在阻挡金属层上形成下电极金属层，然后通过在氮气环境中在大于约650℃的温度下回流下电极金属层来平坦化，以限定较低的电容器电极。 然后在下部电容器电极上形成具有高介电常数的材料层。 然后在电介质层上形成上电容器电极，与下电容器电极相对。 介电层可以包括Ba（Sr，Ti）O3，Pb（Zr，Ti）O3，Ta2O5，SiO2，SiN3，SrTiO3，PZT，SrBi2Ta2O9，（Pb，La）（Zr，Ti）O3和Bi4Ti3O12。 根据本发明的一个实施例，图案化电绝缘层的步骤包括图案化电绝缘层以限定其中露出半导体衬底的表面的接触孔。 形成阻挡金属层的步骤还优选包括在接触孔的侧壁上和基底的暴露面上沉积保形阻挡金属层。 阻挡金属层可以选自TiN，CoSi，TaSiN，TiSiN，TaSi，TiSi，Ta和TaN。

公开(公告)号：US5970309A

公开(公告)日：1999-10-19

申请号：US950887

申请日：1997-10-15

Applicant: Jung-min Ha ,  Byung-lyul Park ,  Dae-hong Ko ,  Sang-in Lee

Inventor： Jung-min Ha ,  Byung-lyul Park ,  Dae-hong Ko ,  Sang-in Lee

IPC: H01L27/04 ,  H01L21/02 ,  H01L21/822 ,  H01L21/8242 ,  H01L27/108

CPC classification number: H01L27/1085 ,  H01L28/60 ,  H01L28/82

Abstract: A method of manufacturing a semiconductor capacitor electrode by growing a metal compound layer over polysilicon storage nodes. The metal compound layer readily growing on the polysilicon storage nodes, but not on portions of an insulating layer between adjacent polysilicon storage nodes.

Abstract translation: 一种通过在多晶硅储存节点上生长金属化合物层来制造半导体电容器电极的方法。 金属化合物层容易生长在多晶硅存储节点上，而不是在相邻的多晶硅存储节点之间的绝缘层的部分上生长。

公开(公告)号：US5939787A

公开(公告)日：1999-08-17

申请号：US929419

申请日：1997-09-15

Applicant: Sang-in Lee

Inventor： Sang-in Lee

IPC: H01L21/28 ,  C23C14/06 ,  C23C14/24 ,  H01L21/768 ,  H01L23/522 ,  H01L23/532 ,  H01L23/48 ,  H01L29/43

CPC classification number: H01L21/76856 ,  H01L21/76843 ,  H01L21/76846 ,  H01L21/76877 ,  H01L21/76882 ,  H01L23/532 ,  H01L2924/0002 ,  Y10S257/915

Abstract: A semiconductor device and manufacturing method thereof having a diffusion barrier layer formed on a semiconductor wafer, whose surface region is provided with a silylation layer, wherein the silylation layer is formed on the diffusion barrier layer which is formed on the semiconductor wafer, by a plasma process using silicon hydride or by a reactive sputtering method using SiH.sub.4. When the metal layer is formed on the silylation layer, the wettability between the diffusion barrier layer and the metal is enhanced and large grains are formed, thereby increasing the step coverage for the contact hole of the metal layer or for the via hole. Additionally, when heat treatment is performed after the metal layer is formed on the silylation layer, the reflow characteristic of the metal layer becomes good, to thereby facilitate the filling of the contact hole or the via hole easy. When the wiring layer is thus formed, the metal wiring having good reliability can be obtained and the subsequent process is rendered unnecessary.

Abstract translation: 一种半导体器件及其制造方法，其具有形成在半导体晶片上的扩散阻挡层，其表面区域设置有甲硅烷基化层，其中所述甲硅烷基层通过等离子体形成在形成在半导体晶片上的扩散阻挡层上 使用硅氢化物或通过使用SiH 4的反应溅射法进行。 当在甲硅烷基层上形成金属层时，扩散阻挡层和金属之间的润湿性增强，并且形成大的晶粒，从而增加金属层或通孔的接触孔的阶梯覆盖。 此外，当在甲硅烷基层上形成金属层之后进行热处理时，金属层的回流特性变好，从而易于使接触孔或通孔的填充。 当这样形成布线层时，可以获得具有良好可靠性的金属布线，并且不需要随后的处理。

公开(公告)号：US5851917A

公开(公告)日：1998-12-22

申请号：US625114

申请日：1996-04-01

Applicant: Sang-in Lee

Inventor： Sang-in Lee

IPC: H01L21/285 ,  H01L21/441 ,  H01L21/48 ,  H01L21/768 ,  H01L23/485 ,  H01L23/522 ,  H01L23/532 ,  H01L21/28

CPC classification number: H01L21/76838 ,  H01L21/76843 ,  H01L21/76856 ,  H01L21/76862 ,  H01L21/76876 ,  H01L21/76877 ,  H01L23/485 ,  H01L23/53223 ,  H01L2924/0002 ,  Y10S257/915

Abstract: A wiring structure of semiconductor device and a method for manufacturing the same which fills up a contact hole of below one half micron. An insulating layer is formed on a semiconductor substrate, and a contact hole or a via hole is formed in the insulating layer. On the insulating layer, a first metal is deposited via a CVD method to form a CVD metal layer or a CVD metal plug filling up the contact hole. Then, the thus-obtained CVD metal layer or the CVD metal plug is heat-treated in a vacuum at a high temperature below the melting point of the first metal, thereby planarizing the surface thereof the CVD metal layer. A second metal is deposited via a sputtering method on the CVD metal layer or on the CVD metal plug to thereby form a sputtered metal layer. The contact hole is filled up with the first metal by the CVD method and then a reliable sputtered metal layer is deposited via a sputtering method. The wiring layer can be used for the semiconductor device of the next generation.

Abstract translation: 半导体器件的布线结构及其制造方法，其填充低于一半微米的接触孔。 绝缘层形成在半导体衬底上，并且在绝缘层中形成接触孔或通孔。 在绝缘层上，通过CVD法沉积第一金属，以形成填充接触孔的CVD金属层或CVD金属塞。 然后，将如此获得的CVD金属层或CVD金属插塞在低于第一金属的熔点的高温下在真空中进行热处理，从而平坦化其CVD金属层的表面。 通过溅射法在CVD金属层或CVD金属插塞上沉积第二种金属，从而形成溅射金属层。 通过CVD法将接触孔填充第一金属，然后通过溅射法沉积可靠的溅射金属层。 布线层可用于下一代的半导体器件。

公开(公告)号：US5723384A

公开(公告)日：1998-03-03

申请号：US713944

申请日：1996-09-13

Applicant: Byung-lyul Park ,  Jung-min Ha ,  Dae-hong Ko ,  Sang-in Lee

Inventor： Byung-lyul Park ,  Jung-min Ha ,  Dae-hong Ko ,  Sang-in Lee

IPC: H01L27/04 ,  H01L21/02 ,  H01L21/31 ,  H01L21/822 ,  H01L21/8242 ,  H01L27/108

CPC classification number: H01L27/10852 ,  H01L27/10817 ,  H01L28/91

Abstract: There is provided a method for manufacturing a capacitor in a semiconductor device including the steps of forming first and second insulating layers with a first contact hole through to a semiconductor substrate, patterning a first conductive layer to form a pedestal portion of a lower electrode, using a patterned third insulating layer selectively forming an upper portion of the lower electrode from a tungsten nitride thin film, and forming an undercut beneath the pedestal portion by wet-etching the second insulating layer.

Abstract translation: 提供了一种用于制造半导体器件中的电容器的方法，包括以下步骤：将具有第一接触孔的第一绝缘层和第二绝缘层形成至半导体衬底，使第一导电层图案化以形成下电极的基座部分，使用 图案化的第三绝缘层，从氮化钨薄膜选择性地形成下部电极的上部，并通过湿式蚀刻第二绝缘层，在底座部分下方形成底切。

公开(公告)号：US5572072A

公开(公告)日：1996-11-05

申请号：US341982

申请日：1994-11-16

Applicant: Sang-in Lee

Inventor： Sang-in Lee

IPC: H01L21/285 ,  H01L21/441 ,  H01L21/48 ,  H01L21/768 ,  H01L23/485 ,  H01L23/522 ,  H01L23/532 ,  H01L29/43 ,  H01L29/41

CPC classification number: H01L21/76838 ,  H01L21/76843 ,  H01L21/76856 ,  H01L21/76862 ,  H01L21/76876 ,  H01L21/76877 ,  H01L23/485 ,  H01L23/53223 ,  H01L2924/0002 ,  Y10S257/915

Abstract: The invention relates to a wiring structure for a semiconductor device and a method for manufacturing the same, which fills up a contact hole of below one half micron. An insulating layer is formed on a semiconductor substrate, and a contact hole is formed in the insulating layer. On the insulating layer, a first metal is deposited via a CVD method to form a CVD metal layer or a CVD metal plug filling up the contact hole. Then, the thus-obtained CVD metal layer or the CVD metal plus is heat-treated in a vacuum at a high temperature below the melting point of the first metal, thereby planarizing the surface of the CVD metal layer. A second metal is deposited via a sputtering method on the CVD metal layer or on the CVD metal plug to thereby form a sputtered metal layer. The contact hole is filled up with the first metal by the CVD method and then a reliable sputtered metal layer is deposited via a sputtering method. The wiring layer can be used for semiconductor devices of the next generation.

公开(公告)号：US5266521A

公开(公告)日：1993-11-30

申请号：US828458

申请日：1992-01-31

Applicant: Sang-in Lee ,  Chang-soo Park ,  Jeong-ha Son

Inventor： Sang-in Lee ,  Chang-soo Park ,  Jeong-ha Son

IPC: H01L21/20 ,  H01L21/3205 ,  H01L21/321 ,  H01L21/768 ,  H01L23/532 ,  H01L21/441

CPC classification number: H01L21/76882 ,  H01L21/32115 ,  H01L21/7684 ,  H01L23/53214 ,  H01L21/76804 ,  H01L2924/0002 ,  Y10S438/913

Abstract: A method for manufacturing a semiconductor device, comprising the steps of forming an insulating interlayer on a semiconductor substrate to provide a semiconductor intermediate product, providing the insulating interlayer with an opening, forming a first metal layer on the semiconductor intermediate product, heat-treating the first metal layer to fill up the opening with the metal, forming a second metal layer on the first metal layer, and then heat-treating the second layer to planarize the metal layer. An alternative embodiment of the invention encompasses a method for manufacturing a semiconductor device, comprising the steps of providing a semiconductor wafer with an opening formed thereon, forming a metal layer on the semiconductor wafer, and then heat-treating the metal layer to fill up the opening with the metal, wherein pure Al or an aluminum alloy having no Si component is used as the metal in forming the metal layer.

Abstract translation: 一种制造半导体器件的方法，包括以下步骤：在半导体衬底上形成绝缘中间层以提供半导体中间产物，为绝缘中间层提供开口，在半导体中间产物上形成第一金属层，热处理 第一金属层用金属填充开口，在第一金属层上形成第二金属层，然后热处理第二层以使金属层平坦化。 本发明的替代实施例包括一种用于制造半导体器件的方法，包括以下步骤：提供半导体晶片，其上形成有开口，在半导体晶片上形成金属层，然后热处理金属层以填充 与金属一起开口，其中在形成金属层时使用纯Al或不含Si成分的铝合金作为金属。

公开(公告)号：US07430751B2

公开(公告)日：2008-09-30

申请号：US11185876

申请日：2005-07-21

Applicant: Sang-in Lee

Inventor： Sang-in Lee

IPC: G11B33/12

CPC classification number: G06F1/184 ,  G06F1/187 ,  G11B25/10 ,  G11B33/022 ,  G11B33/027

Abstract: A data recording/reproducing apparatus that includes an open front housing having a base frame and a cover frame, a recording/reproducing unit installed in the housing to record and/or reproduce data from a predetermined recording medium, a circuit board installed parallel to the recording/reproducing unit in the housing, a front unit connected to the open front of the housing to support operation buttons, a first locking unit which locks the front unit and the recording/reproducing unit, and a second locking unit which locks the front unit and the housing at a position corresponding to the circuit board.

Abstract translation: 一种数据记录/再现装置，包括具有基架和盖框架的开放前壳体，安装在壳体中以从预定记录介质记录和/或再现数据的记录/再现单元，与 记录/再现单元，连接到壳体的开口前部以支撑操作按钮的前单元，锁定前单元和记录/再现单元的第一锁定单元，以及锁定前单元的第二锁定单元 并且在与电路板相对应的位置处的壳体。

公开(公告)号：US20060016671A1

公开(公告)日：2006-01-26

申请号：US10983590

申请日：2004-11-09

Applicant: Sang-in Lee

Inventor： Sang-in Lee

IPC: H01H13/70

CPC classification number: H01H25/041

Abstract: A switching device of an image recording and replaying apparatus, having: a frame with a button sheet having a guide boss opening positioned in a center of the button sheet and operation boss openings positioned around the guide boss opening, pairs of the operation boss openings being oppositely disposed with respect to the guide boss opening; a switchboard placed on a first side of the frame and having tact switches facing respective operation boss openings; an integrated button disposed to be elastically biased toward a second side of the frame opposite the first side, and having a guide boss inserted into the guide boss opening and operation bosses inserted into respective operation boss openings; and a fixation holder disposed on the guide boss to fix the integrated button to the frame, such that the operation bosses continuously contact with corresponding tact switches.

Abstract translation: 一种图像记录和重放装置的切换装置，具有：具有按钮片的框架，其具有位于按钮片的中心的引导凸起开口和位于引导凸起开口周围的操作凸起开口，成对的操作凸起开口为 相对于导向凸起开口相对设置; 布置在所述框架的第一侧上并且具有面向相应的操作凸起开口的触觉开关的开关板; 集成按钮，被设置为朝向与第一侧相对的框架的第二侧弹性偏置，并且具有插入到引导凸台开口中的引导凸起和插入到相应的操作凸起开口中的操作凸起; 以及设置在所述引导凸台上以将所述集成按钮固定到所述框架的固定架，使得所述操作凸台与相应的轻触开关持续接触。