公开(公告)号：US08259495B2

公开(公告)日：2012-09-04

申请号：US13197280

申请日：2011-08-03

Applicant: Satoshi Torii

Inventor： Satoshi Torii

IPC: G11C11/34 ,  G11C16/04 ,  G11C16/06 ,  G11C5/06

CPC classification number: H01L27/11519 ,  G11C16/0416 ,  G11C16/10 ,  H01L27/11526 ,  H01L27/11529 ,  H01L27/11573

Abstract: A semiconductor memory device includes a plurality of memory cell transistors arranged in a matrix; a plurality of word lines commonly coupling the control gates of the plural memory cell transistors present in a identical first direction; a plurality of source lines commonly coupling the sources of the plural memory cell transistors present in the identical first direction; a plurality of bit lines commonly coupling the drains of the plural memory cell transistors present in a identical second direction intersecting the first direction; a first transistor having a drain coupled to the source line; a second transistor having a drain coupled to a source of the first transistor, a gate coupled to the word line and a source grounded; and a control line commonly coupling the gates of the plural first transistors.

Abstract translation: 半导体存储器件包括以矩阵形式布置的多个存储单元晶体管; 多个字线通常耦合存在于相同第一方向上的多个存储单元晶体管的控制栅极; 多个源极线通常耦合存在于相同第一方向上的多个存储单元晶体管的源极; 多个位线通常耦合存在于与第一方向相交的相同第二方向的多个存储单元晶体管的漏极; 第一晶体管，具有耦合到源极线的漏极; 第二晶体管，其具有耦合到所述第一晶体管的源极的漏极，耦合到所述字线的栅极和接地的源极; 以及通常耦合多个第一晶体管的栅极的控制线。

公开(公告)号：US20120195121A1

公开(公告)日：2012-08-02

申请号：US13435901

申请日：2012-03-30

Applicant: Satoshi Torii ,  Kazuhiro Mizutani ,  Toshio Nomura ,  Masayoshi Asano ,  Ikuto Fukuoka ,  Hiroshi Mawatari ,  Motoi Takahashi

Inventor： Satoshi Torii ,  Kazuhiro Mizutani ,  Toshio Nomura ,  Masayoshi Asano ,  Ikuto Fukuoka ,  Hiroshi Mawatari ,  Motoi Takahashi

IPC: G11C16/04

CPC classification number: G11C16/0433 ,  G11C16/10 ,  H01L27/105 ,  H01L27/11526 ,  H01L27/11529

Abstract: A nonvolatile semiconductor memory device including a memory cell array of memory cells arranged in a matrix, each of which includes a selecting transistor and a memory cell transistor; a column decoder controlling the potential of bit lines; a voltage application circuit controlling the potential of the first word lines; a first row decoder controlling the potential of the second word lines; and a second row decoder controlling the potential of the source line. The column decoder is formed of a circuit whose withstand voltage is lower than the voltage application circuit and the second row decoder.

Abstract translation: 一种非易失性半导体存储器件，包括以矩阵形式布置的存储单元阵列，每个存储单元阵列包括选择晶体管和存储单元晶体管; 控制位线电位的列解码器; 电压施加电路，控制第一字线的电位; 控制第二字线的电位的第一行解码器; 以及控制源极线的电位的第二行解码器。 列解码器由耐压低于电压施加电路和第二行解码器的电路形成。

公开(公告)号：US08072806B2

公开(公告)日：2011-12-06

申请号：US12434789

申请日：2009-05-04

Applicant: Satoshi Torii

Inventor： Satoshi Torii

IPC: G11C11/34 ,  G11C16/04 ,  G11C5/06

CPC classification number: H01L27/11519 ,  G11C16/0416 ,  G11C16/10 ,  H01L27/11526 ,  H01L27/11529 ,  H01L27/11573

Abstract: A semiconductor memory device includes a plurality of memory cell transistors arranged in a matrix; a plurality of word lines commonly coupling the control gates of the plural memory cell transistors present in a identical first direction; a plurality of source lines commonly coupling the sources of the plural memory cell transistors present in the identical first direction; a plurality of bit lines commonly coupling the drains of the plural memory cell transistors present in a identical second direction intersecting the first direction; a first transistor having a drain coupled to the source line; a second transistor having a drain coupled to a source of the first transistor, a gate coupled to the word line and a source grounded; and a control line commonly coupling the gates of the plural first transistors.

Abstract translation: 半导体存储器件包括以矩阵形式布置的多个存储单元晶体管; 多个字线通常耦合存在于相同第一方向上的多个存储单元晶体管的控制栅极; 多个源极线通常耦合存在于相同第一方向上的多个存储单元晶体管的源极; 多个位线通常耦合存在于与第一方向相交的相同第二方向的多个存储单元晶体管的漏极; 第一晶体管，具有耦合到源极线的漏极; 第二晶体管，其具有耦合到所述第一晶体管的源极的漏极，耦合到所述字线的栅极和接地的源极; 以及通常耦合多个第一晶体管的栅极的控制线。

公开(公告)号：US20110286257A1

公开(公告)日：2011-11-24

申请号：US13197264

申请日：2011-08-03

Applicant: Satoshi Torii

Inventor： Satoshi Torii

IPC: G11C5/06

CPC classification number: H01L27/11519 ,  G11C16/0416 ,  G11C16/10 ,  H01L27/11526 ,  H01L27/11529 ,  H01L27/11573

Abstract: A semiconductor memory device includes a plurality of memory cell transistors arranged in a matrix; a plurality of word lines commonly coupling the control gates of the plural memory cell transistors present in a identical first direction; a plurality of source lines commonly coupling the sources of the plural memory cell transistors present in the identical first direction; a plurality of bit lines commonly coupling the drains of the plural memory cell transistors present in a identical second direction intersecting the first direction; a first transistor having a drain coupled to the source line; a second transistor having a drain coupled to a source of the first transistor, a gate coupled to the word line and a source grounded; and a control line commonly coupling the gates of the plural first transistors.

Abstract translation: 半导体存储器件包括以矩阵形式布置的多个存储单元晶体管; 多个字线通常耦合存在于相同第一方向上的多个存储单元晶体管的控制栅极; 多个源极线通常耦合存在于相同第一方向上的多个存储单元晶体管的源极; 多个位线通常耦合存在于与第一方向相交的相同第二方向的多个存储单元晶体管的漏极; 第一晶体管，具有耦合到源极线的漏极; 第二晶体管，其具有耦合到所述第一晶体管的源极的漏极，耦合到所述字线的栅极和接地的源极; 以及通常耦合多个第一晶体管的栅极的控制线。

公开(公告)号：US07692236B1

公开(公告)日：2010-04-06

申请号：US11059139

申请日：2005-02-15

Applicant: Michael Brennan ,  Jaeyong Park ,  Hidehiko Shiraiwa ,  Satoshi Torii

Inventor： Michael Brennan ,  Jaeyong Park ,  Hidehiko Shiraiwa ,  Satoshi Torii

IPC: H01L23/62

CPC classification number: H01L29/66833 ,  H01L27/11568 ,  H01L27/11578 ,  H01L29/7923

Abstract: A multiple dual bit integrated circuit system is provided that includes forming first address lines in a semiconductor substrate and forming a charge-trapping layer over the semiconductor substrate. A semiconductor layer is formed over the charge-trapping layer and second address lines are formed in the semiconductor layer to form a plurality of dual bit locations.

Abstract translation: 提供了一种多重双位集成电路系统，其包括在半导体衬底中形成第一地址线并在半导体衬底上形成电荷捕获层。 在电荷俘获层上形成半导体层，并且在半导体层中形成第二地址线以形成多个双位位置。

公开(公告)号：US20080191269A1

公开(公告)日：2008-08-14

申请号：US11997464

申请日：2006-07-21

Applicant: Youseok Suh ,  Satoshi Torii ,  Lei Xue

Inventor： Youseok Suh ,  Satoshi Torii ,  Lei Xue

IPC: H01L29/792

CPC classification number: H01L29/7881 ,  H01L21/28282 ,  H01L29/42324 ,  H01L29/513 ,  H01L29/792

Abstract: A memory device (100) may include a substrate (110), a dielectric layer (210) formed on the substrate (110) and a charge storage element (220) formed on the dielectric layer (210). The memory device (100) may also include an inter-gate dielectric (230) formed on the charge storage element (220), a barrier layer (240) formed on the inter-gate dielectric (230) and a control gate (250) formed on the barrier layer (240). The barrier layer (240) prevents reaction between the control gate (250) and the inter-gate dielectric (230).

Abstract translation: 存储器件（100）可以包括衬底（110），形成在衬底（110）上的电介质层（210）和形成在电介质层（210）上的电荷存储元件（220）。 存储器件（100）还可以包括形成在电荷存储元件（220）上的栅极间电介质（230），形成在栅极间电介质（230）上的阻挡层（240）和控制栅极（250） 形成在阻挡层（240）上。 阻挡层（240）防止控制栅极（250）和栅极间电介质（230）之间的反应。

公开(公告)号：US20070224856A1

公开(公告)日：2007-09-27

申请号：US11714165

申请日：2007-03-06

Applicant: Satoshi Torii ,  Hisataka Yoshimura

Inventor： Satoshi Torii ,  Hisataka Yoshimura

IPC: H05K1/00

CPC classification number: H05K13/0015 ,  H05K3/0008 ,  H05K3/3468 ,  H05K2201/09063 ,  H05K2201/09136 ,  H05K2201/09918 ,  H05K2203/166

Abstract: Disclosed are a positioning method and a board for swiftly and accurately adjusting the position of a warpage-preventive rail for preventing warpage of the board in flow soldering. A mark of a width B provided with a slit having a width A in a direction perpendicular to a dip direction indicated by an arrow is silk-screen printed at an end of a surface opposite to a flow solder surface of a board. The width B of the mark is set to such a value that an operator who adjusts the position can easily recognize the mark. The slit is formed on a surface opposite to a support band where the upper surface of the warpage-preventive rail supports the board, and the width A of the slit is set to a value approximately equal to the width of the upper surface of the warpage-preventive rail.

Abstract translation: 公开了一种定位方法和板，用于快速且精确地调整防翘曲轨道的位置，以防止流动焊接中的板的翘曲。 在与板的流动焊料表面相对的表面的端部处丝网印刷宽度B的标记，该宽度B在与箭头所示的倾斜方向垂直的方向上具有宽度A的狭缝。 标记的宽度B被设置为使得调整位置的操作者可以容易地识别标记的值。 狭缝形成在与防翘曲轨道的上表面支撑基板的支撑带相反的表面上，并且狭缝的宽度A被设定为大致等于翘曲上表面的宽度的值 预防铁路

公开(公告)号：US07238569B2

公开(公告)日：2007-07-03

申请号：US11113508

申请日：2005-04-25

Applicant: Satoshi Torii

Inventor： Satoshi Torii

IPC: H01L21/336

CPC classification number: H01L27/11568 ,  H01L21/28282 ,  H01L27/115

Abstract: Novel fabrication methods permit concurrently forming wordlines, select gates and array source lines in NAND Flash. One method forms oxide and nitride layers of an ONO stack, implants dopants into a source line region to form and unite a source line structure to a source/drain region, forms another oxide and a high-dielectric over the nitride layer, removes the ONOA stack in the source line region, forms a gate oxide in the periphery, and forms an opening in the ONOA stack in an array source line region. The method deposits and selectively removes polysilicon and the high-dielectric concurrently forming wordline and select drain gate structures in bitline contact regions, and select source gate and source line structures in source line regions. The bitline and source line contact regions are implanted to form the source line structure in the source line region and unite the source/drain regions of select source gate structures.

Abstract translation: 新的制造方法允许在NAND Flash中同时形成字线，选择栅极和阵列源极线。 一种方法形成ONO堆叠的氧化物和氮化物层，将掺杂剂注入源极区域以形成源极线结构并将其结合到源极/漏极区域，在氮化物层上形成另一氧化物和高电介质，去除ONOA 堆叠在源极区域中，在周边形成栅极氧化物，并且在阵列源极线区域中的ONOA堆叠中形成开口。 该方法沉积并选择性去除多晶硅和高电介质同时形成字线，并在位线接触区域中选择漏极栅极结构，并在源极线区域中选择源栅极和源极线结构。 植入位线和源极线接触区域以在源极线区域中形成源极线结构，并且将选择源极栅极结构的源极/漏极区域联合起来。

公开(公告)号：US07116582B2

公开(公告)日：2006-10-03

申请号：US11199263

申请日：2005-08-09

Applicant: Satoshi Torii

Inventor： Satoshi Torii

IPC: G11C16/06

CPC classification number: G11C16/3445 ,  G11C16/3436 ,  G11C16/3459

Abstract: A first decision process, which reads data from a memory cell under a first deciding condition to decide pass/fail and applies a signal to the memory cell to change an amount of charge stored in the memory cell if the data is decided as fail, and a second decision process, which reads the data from the memory cell under a second deciding condition that is relaxed rather than the first deciding condition to decide the pass/fail, are executed, and then the processes are repeated from the first decision process when the data is decided as fail in the second decision process.

Abstract translation: 第一判定处理，其在第一判定条件下从存储器单元读取数据以决定通过/失败，并且如果数据被确定为失败则将信号施加到存储器单元以改变存储在存储单元中的电荷量;以及 执行在松弛而不是决定通过/否的第一判定条件的第二判定条件下从存储器单元读取数据的第二判定处理，然后从第一判定处理重复进行处理，当第 在第二决策过程中数据被确定为失败。

公开(公告)号：US07079423B1

公开(公告)日：2006-07-18

申请号：US10896299

申请日：2004-07-20

Applicant: Satoshi Torii

Inventor： Satoshi Torii

IPC: G11C16/04

CPC classification number: G11C16/3427 ,  G11C16/0475 ,  G11C16/12 ,  G11C16/3418

Abstract: The present invention provides a method for programming a selected bit in a memory cell of a non-volatile dual bit flash memory device. The method includes applying a positive voltage to a bit line associated with the selected bit and applying another positive voltage to a word line associated with the selected bit. Next, a positive voltage is applied to a second bit line associated with a complementary bit that shares the memory cell with the selected bit. A positive voltage is also applied to a third bit line that is adjacent to the second bit line and removed from the bit line associated with the selected bit by the second bit line. Applying a negative voltage to the word line then erases the complementary bit, but not its adjacent non-selected bit. The programming cycle is repeated until a desired threshold voltage is obtained.

Abstract translation: 本发明提供了一种用于对非挥发性双位闪速存储器件的存储单元中的选定位进行编程的方法。 该方法包括将正电压施加到与所选位相关联的位线，并将另一正电压施加到与所选位相关联的字线。 接下来，将正电压施加到与所选择的位共享存储器单元的互补位相关联的第二位线。 正电压也被施加到与第二位线相邻的第三位线，并且通过第二位线从与所选位相关联的位线移除。 对字线施加负电压然后擦除互补位，而不是其相邻的未选择位。 重复编程周期，直到获得所需的阈值电压。