公开(公告)号：US08633566B2

公开(公告)日：2014-01-21

申请号：US13089967

申请日：2011-04-19

申请人： Scott E. Sills

发明人： Scott E. Sills

IPC分类号： H01L23/52

CPC分类号： H01L23/5256 ,  H01L27/10 ,  H01L27/1021 ,  H01L27/224 ,  H01L27/24 ,  H01L27/2409 ,  H01L27/2436 ,  H01L2924/0002 ,  H01L2924/00

摘要： A repairable memory cell in accordance with one or more embodiments of the present disclosure includes a storage element positioned between a first and a second electrode, and a repair element positioned between the storage element and at least one of the first electrode and the second electrode.

摘要翻译： 根据本公开的一个或多个实施例的可修复存储单元包括位于第一和第二电极之间的存储元件和位于存储元件与第一电极和第二电极中的至少一个之间的修复元件。

公开(公告)号：US20130175494A1

公开(公告)日：2013-07-11

申请号：US13347840

申请日：2012-01-11

申请人： Dale W. Collins ,  Marko Milojevic ,  Scott E. Sills ,  Si-Young Park

发明人： Dale W. Collins ,  Marko Milojevic ,  Scott E. Sills ,  Si-Young Park

IPC分类号： H01L47/00 ,  H01L21/02

CPC分类号： H01L45/085 ,  H01L45/1233 ,  H01L45/1253 ,  H01L45/1266 ,  H01L45/141 ,  H01L45/145 ,  H01L45/146 ,  H01L45/16

摘要： Memory cells (e.g., CBRAM cells) include an ion source material over an active material and an electrode comprising metal silicide over the ion source material. The ion source material may include at least one of a chalcogenide material and a metal. Apparatuses, such as systems and devices, include a plurality of such memory cells. Memory cells include an adhesion material of metal silicide between a ion source material and an electrode of elemental metal. Methods of forming a memory cell include forming a first electrode, forming an active material, forming an ion source material, and forming a second electrode including metal silicide over the metal ion source material. Methods of adhering a material including copper and a material including tungsten include forming a tungsten silicide material over a material including copper and treating the materials.

摘要翻译： 存储单元（例如，CBRAM单元）包括活性材料上的离子源材料和在离子源材料上的包含金属硅化物的电极。 离子源材料可以包括硫族化物材料和金属中的至少一种。 装置，例如系统和装置，包括多个这样的存储单元。 存储单元包括在离子源材料和元素金属电极之间的金属硅化物的粘附材料。 形成存储单元的方法包括形成第一电极，形成活性材料，形成离子源材料，以及在金属离子源材料上形成包括金属硅化物的第二电极。 包括铜和包括钨的材料的材料的粘合方法包括在包括铜的材料上形成硅化钨材料并处理材料。

公开(公告)号：US20120264272A1

公开(公告)日：2012-10-18

申请号：US13532483

申请日：2012-06-25

申请人： Scott E. Sills ,  Gurtej S. Sandhu

发明人： Scott E. Sills ,  Gurtej S. Sandhu

IPC分类号： H01L21/02

CPC分类号： H01L45/1608 ,  H01L27/2463 ,  H01L45/04 ,  H01L45/06 ,  H01L45/08 ,  H01L45/144 ,  H01L45/146 ,  H01L45/148 ,  H01L45/1683

摘要： A method of forming a nonvolatile memory cell includes forming a first electrode and a second electrode of the memory cell. Sacrificial material is provided between the first second electrodes. The sacrificial material is exchanged with programmable material. The sacrificial material may additionally be exchanged with select device material.

摘要翻译： 形成非易失性存储单元的方法包括形成存储单元的第一电极和第二电极。 牺牲材料设置在第一和第二电极之间。 牺牲材料与可编程材料交换。 牺牲材料可以另外与选择装置材料交换。

公开(公告)号：US20120235106A1

公开(公告)日：2012-09-20

申请号：US13050725

申请日：2011-03-17

申请人： Sanh D. Tang ,  Scott E. Sills ,  Whitney L. West ,  Rob B. Goodwin ,  Nishant Sinha

发明人： Sanh D. Tang ,  Scott E. Sills ,  Whitney L. West ,  Rob B. Goodwin ,  Nishant Sinha

IPC分类号： H01L45/00 ,  H01L21/8239 ,  H01L21/4763

CPC分类号： H01L45/1266 ,  H01L21/7684 ,  H01L21/76843 ,  H01L21/76849 ,  H01L21/76858 ,  H01L21/76877 ,  H01L21/76882 ,  H01L21/76883 ,  H01L23/53247 ,  H01L23/53252 ,  H01L45/04 ,  H01L45/085 ,  H01L45/1233 ,  H01L45/141 ,  H01L45/142 ,  H01L45/143 ,  H01L45/145 ,  H01L45/146 ,  H01L45/16 ,  H01L45/1608 ,  H01L2924/0002 ,  H01L2924/00

摘要： Methods of forming conductive elements, such as interconnects and electrodes, for semiconductor structures and memory cells. The methods include forming a first conductive material and a second conductive material comprising silver in a portion of at least one opening and performing a polishing process to fill the at least one opening with at least one of the first and second conductive materials. An annealing process may be performed to form a mixture or an alloy of the silver and the material. The methods enable formation of silver containing conductive elements having reduced dimensions (e.g., less than about 20 nm). The resulting conductive elements have a desirable resistivity. The methods may be used, for example, to form interconnects for electrically connecting active devices and to form electrodes for memory cells. A semiconductor structure and a memory cell including such a conductive structure are also disclosed.

摘要翻译： 形成用于半导体结构和存储单元的导电元件例如互连和电极的方法。 所述方法包括在至少一个开口的一部分中形成第一导电材料和第二导电材料，所述第二导电材料包括银，并且执行抛光工艺以用至少一个第一和第二导电材料填充所述至少一个开口。 可以进行退火处理以形成银和材料的混合物或合金。 该方法能够形成具有减小的尺寸（例如，小于约20nm）的含银导电元件。 所得的导电元件具有所需的电阻率。 所述方法可以用于例如形成用于电连接有源器件并形成用于存储器单元的电极的互连。 还公开了一种半导体结构和包括这种导电结构的存储单元。

公开(公告)号：US20120046415A1

公开(公告)日：2012-02-23

申请号：US12859869

申请日：2010-08-20

申请人： Dan B. Millward ,  Scott E. Sills

发明人： Dan B. Millward ,  Scott E. Sills

IPC分类号： C08F299/08 ,  C08F299/00

CPC分类号： C08F287/00 ,  C08F8/00 ,  C08F8/42 ,  G03F7/0002 ,  C08F226/06 ,  C08F293/00

摘要： Methods of modifying block copolymers to enhance thermodynamic properties thereof without sacrificing material properties and methods of forming modified block copolymers having desired properties are disclosed. The modified block copolymers may be used, for example, as a mask for sublithographic patterning during various stages of semiconductor device fabrication. For example, block copolymers having desirable material properties, such as etch selectively, may be chemically modified to tailor a χ value thereof to optimize the process conditions for achieving a self-assembled state and to reduce a defectivity of the self-assembled block copolymer pattern.

摘要翻译： 公开了改性嵌段共聚物以提高其热力学性质而不牺牲材料性质的方法和形成具有所需性质的改性嵌段共聚物的方法。 改性嵌段共聚物可以用作例如在半导体器件制造的各个阶段期间用于亚光刻图案的掩模。 例如，具有期望的材料性质的嵌段共聚物，例如选择性蚀刻，可以进行化学修饰以调整其χ值，以优化用于实现自组装状态的工艺条件并降低自组装嵌段共聚物图案的缺陷 。

公开(公告)号：US20120032182A1

公开(公告)日：2012-02-09

申请号：US12853105

申请日：2010-08-09

申请人： Scott E. Sills ,  David R. Jenkins ,  David R. Hembree

发明人： Scott E. Sills ,  David R. Jenkins ,  David R. Hembree

IPC分类号： H01L33/30 ,  H01L21/30 ,  H01L33/60

CPC分类号： H01L25/0753 ,  H01L24/32 ,  H01L24/73 ,  H01L25/167 ,  H01L33/60 ,  H01L33/64 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2924/01322 ,  H01L2924/12043 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2924/00014

摘要： A solid state light (“SSL”), a solid state emitter (“SSE”), and methods of manufacturing SSLs and SSEs. In one embodiment, an SSL comprises a packaging substrate having an electrical contact and a light emitting structure having a front side and a back side. The back side of the light emitting structure is superimposed with the electrical contact of the packaging substrate. The SSL can further include a temperature control element aligned with the light emitting structure and the electrical contact of the packaging substrate.

摘要翻译： 固态光（“SSL”），固态发射器（“SSE”）以及制造SSL和SSEs的方法。 在一个实施例中，SSL包括具有电接触的封装衬底和具有前侧和后侧的发光结构。 发光结构的背面与封装基板的电接触重叠。 SSL还可以包括与发光结构对准的温度控制元件和封装衬底的电接触。

公开(公告)号：US20090226847A1

公开(公告)日：2009-09-10

申请号：US12045373

申请日：2008-03-10

申请人： Yoshiki Hishiro ,  Lijing Gou ,  Scott E. Sills ,  Hiroyuki Mori ,  Paul D. Shirley ,  Troy V. Gugel ,  Adam L. Olson

发明人： Yoshiki Hishiro ,  Lijing Gou ,  Scott E. Sills ,  Hiroyuki Mori ,  Paul D. Shirley ,  Troy V. Gugel ,  Adam L. Olson

IPC分类号： H01L21/47 ,  G03F7/00

CPC分类号： G03F7/7065 ,  G03F7/423

摘要： Reducing or eliminating watermark-type defects during semiconductor device fabrication are described and can comprise treating photoresist using one of several embodiments. In some embodiments, the propensity for defect formation is reduced/eliminated by conditioning the photoresist surface through the application and removal of a sacrificial overcoat. In other embodiments, existing defects are reduced/eliminated by exposing the photoresist surface to a defect-stripping material during post-develop processing.

摘要翻译： 描述了在半导体器件制造期间减少或消除水印型缺陷，并且可以包括使用若干实施例之一来处理光致抗蚀剂。 在一些实施例中，通过施加和去除牺牲外涂层来调节光致抗蚀剂表面来减少/消除缺陷形成的倾向。 在其它实施例中，通过在显影后处理期间将光致抗蚀剂表面暴露于缺陷剥离材料来减少/消除现有缺陷。

公开(公告)号：US10333064B2

公开(公告)日：2019-06-25

申请号：US13086321

申请日：2011-04-13

申请人： Scott E. Sills ,  Gurtej Sandhu

发明人： Scott E. Sills ,  Gurtej Sandhu

IPC分类号： H01L47/00 ,  H01L45/00 ,  H01L27/24

摘要： This disclosure provides embodiments for the formation of vertical memory cell structures that may be implemented in RRAM devices. In one embodiment, memory cell area may be increased by varying word line height and/or word line interface surface characteristics to ensure the creation of a grain boundary that is suitable for formation of conductive pathways through an active layer of an RRAM memory cell. This may maintain continuum behavior while reducing random cell-to-cell variability that is often encountered at nanoscopic scales. In another embodiment, such vertical memory cell structures may be formed in multiple-tiers to define a three-dimensional RRAM memory array. Further embodiments also provide a spacer pitch-doubled RRAM memory array that integrates vertical memory cell structures.

公开(公告)号：US09048415B2

公开(公告)日：2015-06-02

申请号：US13347840

申请日：2012-01-11

申请人： Dale W. Collins ,  Marko Milojevic ,  Scott E. Sills ,  Si-Young Park

发明人： Dale W. Collins ,  Marko Milojevic ,  Scott E. Sills ,  Si-Young Park

IPC分类号： H01L47/00 ,  H01L45/00

CPC分类号： H01L45/085 ,  H01L45/1233 ,  H01L45/1253 ,  H01L45/1266 ,  H01L45/141 ,  H01L45/145 ,  H01L45/146 ,  H01L45/16

摘要： Memory cells (e.g., CBRAM cells) include an ion source material over an active material and an electrode comprising metal silicide over the ion source material. The ion source material may include at least one of a chalcogenide material and a metal. Apparatuses, such as systems and devices, include a plurality of such memory cells. Memory cells include an adhesion material of metal silicide between a ion source material and an electrode of elemental metal. Methods of forming a memory cell include forming a first electrode, forming an active material, forming an ion source material, and forming a second electrode including metal silicide over the metal ion source material. Methods of adhering a material including copper and a material including tungsten include forming a tungsten silicide material over a material including copper and treating the materials.

摘要翻译： 存储单元（例如，CBRAM单元）包括活性材料上的离子源材料和在离子源材料上的包含金属硅化物的电极。 离子源材料可以包括硫族化物材料和金属中的至少一种。 装置，例如系统和装置，包括多个这样的存储单元。 存储单元包括在离子源材料和元素金属电极之间的金属硅化物的粘附材料。 形成存储单元的方法包括形成第一电极，形成活性材料，形成离子源材料，以及在金属离子源材料上形成包括金属硅化物的第二电极。 包括铜和包括钨的材料的材料的粘合方法包括在包括铜的材料上形成硅化钨材料并处理材料。

公开(公告)号：US08759807B2

公开(公告)日：2014-06-24

申请号：US13427529

申请日：2012-03-22

申请人： Gurtej S. Sandhu ,  Scott E. Sills

发明人： Gurtej S. Sandhu ,  Scott E. Sills

IPC分类号： H01L29/00 ,  H01L47/00 ,  H01L29/02 ,  H01L29/04 ,  H01L29/06 ,  H01L47/02

CPC分类号： H01L45/16 ,  H01L27/2463 ,  H01L27/2472 ,  H01L45/04 ,  H01L45/06 ,  H01L45/08 ,  H01L45/085 ,  H01L45/1233 ,  H01L45/1266 ,  H01L45/142 ,  H01L45/143 ,  H01L45/144 ,  H01L45/146 ,  H01L45/147 ,  H01L45/148

摘要： Some embodiments include methods of forming memory cells. An opening is formed over a first conductive structure to expose an upper surface of the first conductive structure. The opening has a bottom level with a bottom width. The opening has a second level over the bottom level, with the second level having a second width which is greater than the bottom width. The bottom level of the opening is filled with a first portion of a multi-portion programmable material, and the second level is lined with the first portion. The lined second level is filled with a second portion of the multi-portion programmable material. A second conductive structure is formed over the second portion. Some embodiments include memory cells.

摘要翻译： 一些实施例包括形成存储器单元的方法。 在第一导电结构上形成开口以暴露第一导电结构的上表面。 开口具有底部底部宽度。 开口具有超过底部水平的第二水平，其中第二水平具有大于底部宽度的第二宽度。 开口的底部水平填充有多部分可编程材料的第一部分，并且第二层与第一部分相衬。 衬里的第二层被多部分可编程材料的第二部分填充。 在第二部分上形成第二导电结构。 一些实施例包括存储器单元。