公开(公告)号：US5063497A

公开(公告)日：1991-11-05

申请号：US69372

申请日：1987-07-01

申请人： David N. Cutler ,  David A. Orbits ,  Dileep Bhandarkar ,  Wayne Cardoza ,  Richard T. Witek

发明人： David N. Cutler ,  David A. Orbits ,  Dileep Bhandarkar ,  Wayne Cardoza ,  Richard T. Witek

IPC分类号： G06F9/38 ,  G06F12/08 ,  G06F15/78 ,  G06F17/16

CPC分类号： G06F9/3865 ,  G06F12/08 ,  G06F15/8069 ,  G06F9/30036

摘要： In a data processing system employing virtual memory techniques and capable of performing a plurality of overlapping scalar and vector data processing operations, apparatus and method are provided to allow continuation of program execution after one or more vector load/store instructions, which refer to data values that are not currently in memory, receive page faults. At the occurrence of such a page fault, all instructions currently in execution are allowed to be completed, whereupon information summarizing the page fault condition is recorded in memory for use by the operating system software and a vector exception is generated. Operating system software responds to this exception, examines the fault information, causes the missing pages to be read into the main memory unit from the mass storage media, re-executes the exception producing vector instruction(s) and continues with the program execution.

公开(公告)号：US07395443B1

公开(公告)日：2008-07-01

申请号：US11023792

申请日：2004-12-28

申请人： Stephen C. Kromer ,  James J. Montanaro ,  Richard T. Witek ,  Kathryn J. Hoover

发明人： Stephen C. Kromer ,  James J. Montanaro ,  Richard T. Witek ,  Kathryn J. Hoover

IPC分类号： G06F1/32

CPC分类号： G06F1/3203 ,  G06F1/3287 ,  Y02D10/171

摘要： An integrated circuit (100) includes a firewall input terminal, a first circuit (110, 120, 170, 172), and a second circuit (220). The firewall input terminal is for receiving a firewall input signal. The first circuit (110, 120, 170, 172) is coupled to a first power supply voltage terminal (203) and has an output for providing a control signal. The second circuit is coupled to a second power supply voltage terminal (210), to the firewall input terminal (214), and to the first circuit (110, 120, 170, 172). When the firewall input signal is inactive, an activation of the control signal affects the operation of the second circuit. When the firewall input signal is active, an activation of the control signal does not affect the operation of the second circuit.

摘要翻译： 集成电路（100）包括防火墙输入端，第一电路（110,120,170,172）和第二电路（220）。 防火墙输入端子用于接收防火墙输入信号。 第一电路（110,120,170,172）耦合到第一电源电压端子（203），并且具有用于提供控制信号的输出。 第二电路被耦合到第二电源电压端子（210），到防火墙输入端子（214）和第一电路（110,120,170,172）。 当防火墙输入信号无效时，控制信号的激活会影响第二个电路的运行。 当防火墙输入信号有效时，控制信号的激活不会影响第二个电路的运行。

公开(公告)号：US5291581A

公开(公告)日：1994-03-01

申请号：US844968

申请日：1992-02-28

申请人： David N. Cutler ,  David A. Orbits ,  Dileep Bhandarkar ,  Wayne Cardoza ,  Richard T. Witek

发明人： David N. Cutler ,  David A. Orbits ,  Dileep Bhandarkar ,  Wayne Cardoza ,  Richard T. Witek

IPC分类号： G06F9/46 ,  G06F15/78 ,  G06F12/14

CPC分类号： G06F9/52 ,  G06F15/8069

摘要： In a multiprocessor data processing unit, a data element in the main memory unit, that has system wide significance, can have a requirement that this data element be altered in a controlled manner. Because other data processing units can have access to this data element, the alteration of the data element must be synchronized so the other data processing units are not in the process of altering the same data element simultaneously. The present invention includes an instruction that acquires access to an interlock signal in the main memory unit and initiates an interlock in the main memory unit, thereby excluding other data processing units from gaining access to the interlock signal simultaneously. The instruction causes the data element related to the interlock signal to be transferred to the data processing unit where the data element is saved, can be entered in mask apparatus and then have a quantity added thereto. The altered data element is returned to the main memory unit location and the main memory interlock signal is released, thereby completing the instruction.

摘要翻译： 在多处理器数据处理单元中，具有系统广泛意义的主存储单元中的数据元素可以要求以受控的方式改变该数据元素。 因为其他数据处理单元可以访问该数据元素，所以数据元素的改变必须被同步，以便其他数据处理单元不会同时改变相同的数据元素。 本发明包括获取对主存储器单元中的联锁信号的访问并且在主存储器单元中启动互锁的指令，从而排除其他数据处理单元以同时访问互锁信号。 该指令使与互锁信号相关的数据元素被传送到数据元素被保存的数据处理单元，可以进入掩模装置，然后添加一个数量。 更改的数据元素返回到主存储器单元位置，并且主存储器互锁信号被释放，从而完成指令。

公开(公告)号：US07093153B1

公开(公告)日：2006-08-15

申请号：US10284763

申请日：2002-10-30

申请人： Richard T. Witek ,  Suzanne Plummer ,  James Joseph Montanaro ,  Stephen Charles Kromer ,  Kathryn Jean Hoover

发明人： Richard T. Witek ,  Suzanne Plummer ,  James Joseph Montanaro ,  Stephen Charles Kromer ,  Kathryn Jean Hoover

IPC分类号： G06F1/08

CPC分类号： G06F1/08 ,  G06F1/3203 ,  G06F1/324 ,  G06F1/3253 ,  Y02D10/126 ,  Y02D10/151

摘要： A data processing system (100) comprises a system bus (120), a plurality of devices (110, 150, 160, 170) coupled to the system bus (120), a bus monitor circuit (140), and a clock generator (130). The plurality of devices (110, 150, 160, 170) includes at least one bus master (110, 150) which is capable of performing accesses on the system bus (120). The bus monitor circuit (140) is coupled to the at least one bus master (110, 150), and has an output for providing a bus idle signal to indicate that no bus master is attempting to perform an access on the system bus (120). The clock generator (130) has an output coupled to at least one of the plurality of devices (110, 150, 160, 170) and provides a bus clock signal having a first frequency when the bus idle signal is inactive and having a second frequency lower than the first frequency when the bus idle signal is active.

摘要翻译： 数据处理系统（100）包括系统总线（120），耦合到系统总线（120）的多个设备（110,150,160,170），总线监控电路（140）和时钟发生器 130）。 多个设备（110,150,160,170）包括能够在系统总线（120）上执行访问的至少一个总线主机（110,150）。 总线监视器电路（140）耦合到至少一个总线主机（110,150），并且具有用于提供总线空闲信号的输出，以指示没有总线主控器正在尝试在系统总线上执行访问（120 ）。 时钟发生器（130）具有耦合到多个设备（110,150,160,170）中的至少一个的输出端，并且当总线空闲信号无效并具有第二频率时提供具有第一频率的总线时钟信号 当总线空闲信号有效时低于第一频率。

公开(公告)号：US06076158A

公开(公告)日：2000-06-13

申请号：US86354

申请日：1993-07-01

申请人： Richard Lee Sites ,  Richard T. Witek

发明人： Richard Lee Sites ,  Richard T. Witek

IPC分类号： G06F9/315 ,  G06F9/32 ,  G06F9/38

CPC分类号： G06F9/30072 ,  G06F9/30032 ,  G06F9/322 ,  G06F9/324 ,  G06F9/3846

摘要： A CPU of the RISC type employs a standardized, fixed instruction size, and permits only simplified memory access data width and addressing modes limited to register-to-register operations and register load/store operations. Byte manipulation instructions include the facility for doing in-register byte extract, insert and masking, along with non-aligned load and store instructions. The load/locked and store/conditional instructions permits the implementation of atomic byte writes. By providing a conditional move instruction, many short branches can be eliminated altogether. A conditional move instruction tests a register and moves a second register to a third if the condition is met; this function can be substituted for short branches and thus maintain the sequentiality of the instruction stream. Performance can be speeded up by predicting the target of a branch and prefetching the new instruction based upon this prediction; a branch prediction rule is followed that requires all forward branches to be predicted not-taken and all backward branches to be predicted as taken. Another embodiment uses unused bits in the standard-sized instruction to provide a hint of the expected target address for jump and jump to subroutine instructions or the like. The target can thus be prefetched before the actual address has been calculated and placed in a register. In addition, the unused displacement part of the jump instruction can contain a field to define the actual type of jump, i.e., jump, jump to subroutine, return from subroutine, and thus place a predicted target address in a stack to allow prefetching before the instruction has been executed. The processor can employ a variable memory page size, so that the entries in a translation buffer for implementing virtual addressing can be optimally used. A granularity hint is added to the page table entry to define the page size for this entry. An additional feature is the addition of a prefetch instruction which serves to move a block of data to a faster-access cache in the memory hierarchy before the data block is to be used.

公开(公告)号：US5778423A

公开(公告)日：1998-07-07

申请号：US547630

申请日：1990-06-29

申请人： Richard Lee Sites ,  Richard T. Witek

发明人： Richard Lee Sites ,  Richard T. Witek

IPC分类号： G06F9/30 ,  G06F9/318 ,  G06F9/38 ,  G06F12/08

CPC分类号： G06F9/30072 ,  G06F12/0862 ,  G06F9/30014 ,  G06F9/30025 ,  G06F9/3004 ,  G06F9/30047 ,  G06F9/30087 ,  G06F9/30145 ,  G06F9/30167 ,  G06F9/30185 ,  G06F9/324 ,  G06F9/383 ,  G06F9/3834 ,  G06F9/3846 ,  G06F2212/6028

摘要： A high-performance CPU of the RISC (reduced instruction set) type employs a standardized, fixed instruction size, and permits only simplified memory access data width and addressing modes. The instruction set is limited to register-to-register operations and register load/store operations. Byte manipulation instructions, included to permit use of previously-established data structures, include the facility for doing in-register byte extract, insert and masking, along with non-aligned load and store instructions. The provision of load/locked and store/conditional instructions permits the implementation of atomic byte writes. By providing a conditional move instruction, many short branches can be eliminated altogether. A conditional move instruction tests a register and moves a second register to a third if the condition is met; this function can be substituted for short branches and thus maintain the sequentiality of the instruction stream. Performance can be speeded up by predicting the target of a branch and prefetching the new instruction based upon this prediction; a branch prediction rule is followed that requires all forward branches to be predicted not-taken and all backward branches (as is common for loops) to be predicted as taken. Another performance improvement makes use of unused bits in the standard-sized instruction to provide a hint of the expected target address for jump and jump to subroutine instructions or the like. The target can thus be prefetched before the actual address has been calculated and placed in a register. In addition, the unused displacement part of the jump instruction can contain a field to define the actual type of jump, i.e., jump, jump to subroutine, return from subroutine, and thus place a predicted target address in a stack to allow prefetching before the instruction has been executed. The processor can employ a variable memory page size, so that the entries in a translation buffer for implementing virtual addressing can be optimally used. A granularity hint is added to the page table entry to define the page size for this entry. An additional feature is the addition of a prefetch instruction which serves to move a block of data to a faster-access cache in the memory hierarchy before the data block is to be used.

公开(公告)号：US07750912B2

公开(公告)日：2010-07-06

申请号：US11286690

申请日：2005-11-23

申请人： R. Stephen Polzin ,  Richard T. Witek ,  Maurice B. Steinman

发明人： R. Stephen Polzin ,  Richard T. Witek ,  Maurice B. Steinman

IPC分类号： G09G5/36

CPC分类号： G06F1/3293 ,  G06F1/3203 ,  G06F1/3218 ,  G06F1/325 ,  G06F15/7807 ,  Y02D10/122 ,  Y02D50/20

摘要： In one embodiment, a system comprises a memory; a memory interface coupled to the memory; a processor unit coupled to the memory interface, a second interface coupled to the processor unit, and a graphics processing unit. The processor unit comprises at least one processor core and a display controller configured to couple to a display. The graphics processing unit is configured to render data into a frame buffer representing an image to be displayed on the display. The processor unit is configured to deactivate the second interface if the graphics processing unit is not rendering, and the display controller is configured to read the frame buffer data for display even if the second interface is deactivated.

摘要翻译： 在一个实施例中，系统包括存储器; 耦合到存储器的存储器接口; 耦合到存储器接口的处理器单元，耦合到处理器单元的第二接口和图形处理单元。 处理器单元包括至少一个处理器核心和被配置为耦合到显示器的显示控制器。 图形处理单元被配置为将数据呈现到表示要在显示器上显示的图像的帧缓冲器。 如果图形处理单元不呈现，则处理器单元被配置为停用第二接口，并且即使第二接口被停用，显示控制器被配置为读取用于显示的帧缓冲器数据以进行显示。

公开(公告)号：US5995746A

公开(公告)日：1999-11-30

申请号：US661196

申请日：1996-06-10

申请人： Richard Lee Sites ,  Richard T. Witek

发明人： Richard Lee Sites ,  Richard T. Witek

IPC分类号： G06F9/305 ,  G06F9/30

CPC分类号： G06F9/30032 ,  G06F9/30 ,  G06F9/30021 ,  G06F9/30036 ,  G06F9/30072

摘要： A high-performance CPU of the RISC (reduced instruction set) type employs a standardized, fixed instruction size, and permits only simplified memory access data width and addressing modes. The instruction set is limited to register-to-register operations and register load/store operations. Byte manipulation instructions, included to permit use of previously-established data structures, include the facility for doing in-register byte extract, insert and masking, along with non-aligned load and store instructions. The provision of load/locked and store/conditional instructions permits the implementation of atomic byte writes. By providing a conditional move instruction, many short branches can be eliminated altogether. A conditional move instruction tests a register and moves a second register to a third if the condition is met; this function can be substituted for short branches and thus maintain the sequentiality of the instruction stream.

摘要翻译： RISC（精简指令集）类型的高性能CPU采用标准化的固定指令大小，并且仅允许简化的存储器访问数据宽度和寻址模式。 指令集仅限于寄存器到寄存器操作和寄存器加载/存储操作。 包括允许使用先前建立的数据结构的字节操作指令包括进行寄存器中字节提取，插入和屏蔽以及非对齐加载和存储指令的功能。 提供加载/锁定和存储/条件指令允许实现原子字节写入。 通过提供条件移动指令，可以完全消除许多短分支。 条件移动指令测试寄存器，并且如果满足条件则将第二寄存器移动到第三寄存器; 该功能可以代替短分支，从而保持指令流的顺序性。

公开(公告)号：US5341482A

公开(公告)日：1994-08-23

申请号：US995341

申请日：1992-12-22

申请人： David N. Cutler ,  David A. Orbits ,  Dileep Bhandarkar ,  Wayne Cardoza ,  Richard T. Witek

发明人： David N. Cutler ,  David A. Orbits ,  Dileep Bhandarkar ,  Wayne Cardoza ,  Richard T. Witek

IPC分类号： G06F9/38 ,  G06F9/30 ,  G06F9/34 ,  G06F13/376

CPC分类号： G06F9/3861

摘要： An instruction eases exception handling in a data processing system having one or more parallel pipelined execution units by permitting the central processing unit to complete instructions currently being processed by the execution units, but preventing further instructions from being initiated until all currently executing instructions have been completed and all outstanding exception conditions have been resolved. After all the instructions preceding the DRAIN instruction of the present invention in the program instruction sequence have been executed, the central processing unit can continue to execute the sequential program instructions when no arithmetic exception has been identified, or can invoke an exception handling procedure when an arithmetic exception has been identified. The instruction is typically positioned in an instruction sequence after an instruction that has high degree of probability of resulting in the identification of an arithmetic exception condition. The DRAIN instruction permits the source of the exception to be localized and permits the response to all arithmetic exceptions associated with instructions initiated before the DRAIN instruction, but identified after the execution of the DRAIN instruction, to be handled in the same context environment in which the instruction was initiated.

摘要翻译： 一种指令通过允许中央处理单元完成由执行单元正在处理的指令，但是在所有当前执行的指令已经完成之前阻止进一步的指令被启动，从而简化了具有一个或多个并行流水线执行单元的数据处理系统中的异常处理 所有突出的例外情况都已经解决。 在程序指令序列中本发明的DRAIN指令之前的所有指令已被执行之后，当没有识别出算术异常时，中央处理单元可以继续执行顺序程序指令，或者当调用异常处理程序时 算术异常已被识别。 指令通常位于指令序列之后，该指令具有导致算术异常条件的识别的高概率概率。 DRAIN指令允许异常源被本地化，并且允许对在DRAIN指令之前发起的指令相关联的所有算术异常进行响应，但在执行DRAIN指令之后识别，以在相同的上下文环境中处理，其中 教学开始了。

公开(公告)号：US5043886A

公开(公告)日：1991-08-27

申请号：US245263

申请日：1988-09-16

申请人： Richard T. Witek ,  George M. Uhler

发明人： Richard T. Witek ,  George M. Uhler

IPC分类号： G06F12/08 ,  G06F15/16

CPC分类号： G06F12/0804 ,  G06F12/0815

摘要： A method for reading data blocks from main memory by central processing units in a multiprocessor system containing write-back caches. Load or gather instructions contain a write-intent flag. The status of the write-intent flag is determined. It is also determined whether a data block requested in the instruction by one of the processors is located in a corresponding cache, and if so, the requested data block is returned to the processor. If the data block is not in the cache and the write-intent flag indicates that the block will not be modified, the data block is read from main memory without obtaining a write privilege. The requested data block is subsequently returned from the cache to the processor. If the data block is not in the cache and the write-intent flag indicates the data block will be modified by the processor, then the data block is read from main memory while obtaining the write privilege. Subsequently, the requested data block is returned from the cache to the processor.