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184 条记录 (耗时 0.041 秒)

    Alignment mark for opaque layer
    11.
    发明授权
    Alignment mark for opaque layer 有权
    不透明层的对齐标记

    公开(公告)号：US08324742B2

    公开(公告)日：2012-12-04

    申请号：US12185003

    申请日：2008-08-01

    申请人： Scott R. Summerfelt ,  Stephen A. Meisner ,  John B. Robbins

    发明人： Scott R. Summerfelt ,  Stephen A. Meisner ,  John B. Robbins

    IPC分类号： H01L23/544 ,  H01L21/76

    CPC分类号： H01L23/544 ,  H01L2223/54426 ,  H01L2223/54453 ,  H01L2223/5448 ,  H01L2924/0002 ,  H01L2924/00

    摘要： An IC alignment mark in a contact metal layer for use under an opaque layer, and a process for forming the alignment mark, are disclosed. The alignment mark includes contact metal fields, each several microns wide, with an array of PMD pillars in the interior, formed during contact etch, contact metal deposition and selective contact metal removal processes. The pillars are arrayed such that all exposed surfaces of the contact metal are planar. One configuration is a rectangular array in which every other row is laterally offset by one-half of the column spacing. Horizontal dimensions of the pillars are selected to maximize the contact metal fill factor, while providing sufficient adhesion to the underlying substrate during processing. The contact metal is at least 15 nanometers lower than the PMD layer surrounding the alignment mark, as a result of the contact metal removal process.

    摘要翻译： 公开了在不透明层下使用的接触金属层中的IC对准标记和用于形成对准标记的工艺。 对准标记包括几微米宽的接触金属场，在接触蚀刻期间形成的PMD柱阵列，接触金属沉积和选择性接触金属去除过程。 柱子被排列成使得接触金属的所有暴露表面是平面的。 一个配置是矩形阵列，其中每隔一行被横向偏移列间距的一半。 选择柱的水平尺寸以使接触金属填充因子最大化，同时在处理期间向下面的基底提供足够的粘附。 作为接触金属去除过程的结果，接触金属比围绕对准标记的PMD层低至少15纳米。

    Method for leakage reduction in fabrication of high-density FRAM arrays
    12.
    发明授权
    Method for leakage reduction in fabrication of high-density FRAM arrays 有权
    高密度FRAM阵列制造中泄漏减少的方法

    公开(公告)号：US08093070B2

    公开(公告)日：2012-01-10

    申请号：US11706722

    申请日：2007-02-15

    申请人： Francis Gabriel Celii ,  Kezhakkedath R. Udayakumar ,  Gregory B. Shinn ,  Theodore S. Moise ,  Scott R. Summerfelt

    发明人： Francis Gabriel Celii ,  Kezhakkedath R. Udayakumar ,  Gregory B. Shinn ,  Theodore S. Moise ,  Scott R. Summerfelt

    IPC分类号： H01L21/00

    CPC分类号： H01L28/75 ,  H01L27/11507 ,  H01L28/55

    摘要： A method is provided for fabricating a ferroelectric capacitor structure including a method for etching and cleaning patterned ferroelectric capacitor structures in a semiconductor device. The method comprises etching portions of an upper electrode, etching ferroelectric material, and etching a lower electrode to define a patterned ferroelectric capacitor structure, and etching a portion of a lower electrode diffusion barrier structure. The method further comprises ashing the patterned ferroelectric capacitor structure using a first ashing process, where the ash comprises an oxygen/nitrogen/water-containing ash, performing a wet clean process after the first ashing process, and ashing the patterned ferroelectric capacitor structure using a second ashing process.

    摘要翻译： 提供一种用于制造铁电电容器结构的方法，其包括在半导体器件中蚀刻和清洁图案化的铁电电容器结构的方法。 该方法包括蚀刻上电极的部分，蚀刻铁电材料，并蚀刻下电极以限定图案化的铁电电容器结构，以及蚀刻下电极扩散阻挡结构的一部分。 所述方法还包括使用第一灰化过程灰化所述图案化的铁电电容器结构，其中所述灰分包括含氧/氮/水的灰分，在所述第一灰化处理之后执行湿式清洁处理，以及使用 第二次灰化过程。

    Increasing Exposure Tool Alignment Signal Strength for a Ferroelectric Capacitor Layer
    15.
    发明申请
    Increasing Exposure Tool Alignment Signal Strength for a Ferroelectric Capacitor Layer 有权
    增加铁电电容层的曝光工具对准信号强度

    公开(公告)号：US20110014360A1

    公开(公告)日：2011-01-20

    申请号：US12889851

    申请日：2010-09-24

    申请人： Stephen Arion Meisner ,  Scott R. Summerfelt

    发明人： Stephen Arion Meisner ,  Scott R. Summerfelt

    IPC分类号： H05K3/00

    CPC分类号： H01L23/544 ,  G03F9/7076 ,  G03F9/7084 ,  H01L2223/54453 ,  H01L2924/0002 ,  Y10T29/42 ,  H01L2924/00

    摘要： An improved alignment structure for photolithographic pattern alignment is disclosed. A topographical alignment mark in an IC under a low reflectivity layer may be difficult to register. A reflective layer is formed on top of the low reflectivity layer so that the topography of the alignment mark is replicated in the reflective layer, enabling registration of the alignment mark using common photolithographic scanners and steppers. The reflective layer may be one or more layers, and may be metallic, dielectric or both. The reflective layer may be global over the entire IC or may be local to the alignment mark area. The reflective layer may be removed during subsequent processing, possibly with assist from an added etch stop layer, or may remain in the completed IC. The disclosed alignment mark structure is applicable to an IC with a stack of ferroelectric capacitor materials.

    摘要翻译： 公开了用于光刻图案对准的改进的对准结构。 在低反射率层下的IC中的地形对准标记可能难以注册。 在低反射层的顶部形成反射层，使得对准标记的形貌在反射层中复制，使得能够使用普通的光刻扫描器和步进器对准对准标记。 反射层可以是一个或多个层，并且可以是金属的，电介质的或两者的。 反射层可以在整个IC上是全局的，或者可以是对准标记区域的局部。 可以在随后的处理期间去除反射层，可能来自添加的蚀刻停止层的辅助，或者可以保留在完整的IC中。 所公开的对准标记结构可应用于具有堆叠铁电电容器材料的IC。

    FeRAM capacitor post stack etch clean/repair
    17.
    发明授权
    FeRAM capacitor post stack etch clean/repair 有权
    FeRAM电容器堆栈蚀刻清洁/修复

    公开(公告)号：US06656748B2

    公开(公告)日：2003-12-02

    申请号：US10125662

    申请日：2002-04-18

    申请人： Lindsey H. Hall ,  Scott R. Summerfelt

    发明人： Lindsey H. Hall ,  Scott R. Summerfelt

    IPC分类号： H01L2100

    CPC分类号： H01L21/31122 ,  H01L21/31691 ,  H01L21/32136 ,  H01L27/105 ,  H01L27/11502 ,  H01L27/11507 ,  H01L27/11509 ,  H01L28/55

    摘要： The present invention is directed to a method of forming an FeRAM integrated circuit, which includes performing a capacitor stack etch to define the FeRAM capacitor. The method comprises etching a PZT ferroelectric layer with a high temperature BCl3 etch which provides substantial selectivity with respect to the hard mask. Alternatively, the PZT ferroelectric layer is etch using a low temperature fluorine component etch chemistry such as CHF3 to provide a non-vertical PZT sidewall profile. Such a profile prevents conductive material associated with a subsequent bottom electrode layer etch from depositing on the PZT sidewall, thereby preventing leakage or a “shorting out” of the resulting FeRAM capacitor.

    摘要翻译： 本发明涉及形成FeRAM集成电路的方法，其包括执行电容器堆叠蚀刻以限定FeRAM电容器。 该方法包括用提供相对于硬掩模的实质选择性的高温BCl3蚀刻来蚀刻PZT铁电层。 或者，PZT铁电层是使用诸如CHF 3的低温氟成分蚀刻化学品进行蚀刻以提供非垂直PZT侧壁轮廓。 这种轮廓防止与随后的底部电极层蚀刻相关联的导电材料沉积在PZT侧壁上，从而防止所得FeRAM电容器的泄漏或“短路”。

    Lightly donor doped electrodes for high-dielectric-constant materials
    18.
    发明授权
    Lightly donor doped electrodes for high-dielectric-constant materials 失效
    用于高介电常数材料的轻掺杂掺杂电极

    公开(公告)号：US06593638B1

    公开(公告)日：2003-07-15

    申请号：US08477957

    申请日：1995-06-07

    申请人： Scott R. Summerfelt ,  Howard R. Beratan ,  Bruce Gnade

    发明人： Scott R. Summerfelt ,  Howard R. Beratan ,  Bruce Gnade

    IPC分类号： H01L2900

    CPC分类号： H01G4/008 ,  H01L21/31691 ,  H01L27/11502 ,  H01L28/56 ,  Y10S257/917 ,  Y10T29/43 ,  Y10T29/435

    摘要： A preferred embodiment of this invention comprises a conductive lightly donor doped perovskite layer (e.g. lightly La doped BST 34), and a high-dielectric-constant material layer (e.g. undoped BST 36) overlaying the conductive lightly donor doped perovskite layer. The conductive lightly donor doped perovskite layer provides a substantially chemically and structurally stable electrical connection to the high-dielectric-constant material layer. A lightly donor doped perovskite generally has much less resistance than undoped, acceptor doped, or heavily donor doped HDC materials. The amount of donor doping to make the material conductive (or resistive) is normally dependent on the process conditions (e.g. temperature, atmosphere, grain size, film thickness and composition). This resistivity may be further decreased if the perovskite is exposed to reducing conditions. The lightly donor doped perovskite can be deposited and etched by effectively the same techniques that are developed for the high-dielectric-constant material. The same equipment may used to deposit and etch both the perovskite electrode and the dielectric. These structures may also be used for multilayer capacitors and other thin-film ferroelectric devices such as pyroelectric materials, non-volatile memories, thin-film piezoelectric and thin-film electro-optic oxides.

    摘要翻译： 本发明的优选实施方案包括导电轻掺杂的钙钛矿层（例如轻掺杂的La掺杂的BST 34）和覆盖导电的轻掺杂的钙钛矿层的高介电常数材料层（例如未掺杂的BST 36）。 导电轻掺杂的钙钛矿层提供了与高介电常数材料层基本上化学和结构稳定的电连接。 掺杂的轻掺杂钙钛矿的电阻通常比未掺杂，受体掺杂或重掺杂的HDC材料具有更低的电阻。 导电（或电阻）材料的施主掺杂量通常取决于工艺条件（例如温度，气氛，晶粒尺寸，膜厚度和组成）。 如果钙钛矿暴露于还原条件下，该电阻率可以进一步降低。 通过有效地为高介电常数材料开发的相同技术，可以沉积和蚀刻轻掺杂的钙钛矿。 相同的设备可用于沉积和蚀刻钙钛矿电极和电介质。 这些结构也可以用于多层电容器和其他薄膜铁电体器件，例如热电材料，非易失性存储器，薄膜压电和薄膜电光氧化物。

    Ferroelectric transistors using thin film semiconductor gate electrodes
    20.
    发明授权
    Ferroelectric transistors using thin film semiconductor gate electrodes 有权
    使用薄膜半导体栅电极的铁电晶体管

    公开(公告)号：US06362499B1

    公开(公告)日：2002-03-26

    申请号：US09645158

    申请日：2000-08-24

    申请人： Theodore S. Moise ,  Scott R. Summerfelt

    发明人： Theodore S. Moise ,  Scott R. Summerfelt

    IPC分类号： H01L2976

    CPC分类号： G11C29/44 ,  G11C11/223 ,  G11C2029/1208 ,  H01L21/28291 ,  H01L29/78391

    摘要： A ferroelectric structure on an integrated circuit and methods of making and using the same are disclosed, which may be used, for instance, in a high-speed, non-volatile, non-destructive readout random-access memory device. Generally, the ferroelectric structure combines a thin film ferroelectric variable resistor and a substrate (e.g. silicon) transistor, using a semiconducting film which is common to both. A field effect transistor 26 integrated into substrate 30 has a gate oxide 36 and a semiconducting gate electrode 38 with electrical connections at a first end 44 and a second end 46. Overlying gate electrode 38 is a ferroelectric thin film 40 and a conductive electrode 42. The polarization of ferroelectric thin film 40 is set by applying an appropriate voltage between gate electrode 38 and conductive electrode 42. The polarization of ferroelectric thin film 40 may be subsequently determined by applying a read voltage to 42 and 44, thus causing a voltage V2 to appear at 46 which is determined by the polarization of the ferroelectric variable resistor formed by 38 and 40. Since 38 also forms the gate electrode for field effect transistor 26, the magnitude of V2 affects the magnitude of current I2. Thus I2 is effectively an amplified signal related to the ferroelectric variable resistance which may be read without perturbing the polarization of ferroelectric thin film 40.

    摘要翻译： 公开了集成电路中的铁电结构及其制造和使用的方法，其可以用于例如高速，非易失性，非破坏性读出随机存取存储器件中。 通常，铁电结构使用两者共同的半导体膜组合薄膜铁电可变电阻器和衬底（例如硅）晶体管。 集成到基板30中的场效应晶体管26具有在第一端44和第二端46具有电连接的栅极氧化物36和半导体栅电极38.叠层栅电极38是铁电薄膜40和导电电极42。 通过在栅电极38和导电电极42之间施加适当的电压来设定铁电薄膜40的极化。随后可以通过将读电压施加到42和44来确定铁电薄膜40的极化，从而使电压V2 出现在46处，其由38和40形成的铁电可变电阻器的极化决定。由于38还形成场效应晶体管26的栅电极，因此V2的大小影响电流I2的大小。 因此，I2实际上是与铁电可变电阻相关的放大信号，其可以在不扰乱铁电薄膜40的极化的情况下读取。