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    Semiconductor device
    11.
    发明授权
    Semiconductor device 有权

    公开(公告)号：US09882058B2

    公开(公告)日：2018-01-30

    申请号：US14258466

    申请日：2014-04-22

    Applicant: Semiconductor Energy Laboratory Co., Ltd.

    Inventor： Daisuke Matsubayashi ,  Toshimitsu Obonai ,  Noritaka Ishihara ,  Shunpei Yamazaki

    IPC: H01L27/12 ,  H01L29/786

    CPC classification number: H01L29/7869

    Abstract: A semiconductor device in which variation in electrical characteristics between transistors is reduced is provided. A transistor where a channel is formed in an oxide semiconductor layer is included, and a concentration of carriers contained in a region where the channel is formed in the oxide semiconductor layer is lower than or equal to 1×1015/cm3, preferably lower than or equal to 1×1013/cm3, more preferably lower than or equal to 1×1011/cm3, whereby an energy barrier height which electrons flowing between a source and a drain should go over converges at a constant value. In this manner, a semiconductor device in which variation in the electrical characteristics between the transistors is inhibited is provided.

    Semiconductor device
    12.
    发明授权
    Semiconductor device 有权

    公开(公告)号：US09842940B2

    公开(公告)日：2017-12-12

    申请号：US15062268

    申请日：2016-03-07

    Applicant: Semiconductor Energy Laboratory Co., Ltd.

    Inventor： Shinya Sasagawa ,  Motomu Kurata ,  Kazuya Hanaoka ,  Yoshiyuki Kobayashi ,  Daisuke Matsubayashi

    IPC: H01L29/78 ,  H01L29/786 ,  H01L29/04 ,  H01L29/24

    CPC classification number: H01L29/78696 ,  H01L29/045 ,  H01L29/24 ,  H01L29/7869

    Abstract: A semiconductor device with favorable electrical characteristics is provided. The semiconductor device includes an insulating layer, a semiconductor layer over the insulating layer, a source electrode layer and a drain electrode layer electrically connected to the semiconductor layer, a gate insulating film over the semiconductor layer, the source electrode layer, and the drain electrode layer, and a gate electrode layer overlapping with part of the semiconductor layer, part of the source electrode layer, and part of the drain electrode layer with the gate insulating film therebetween. A cross section of the semiconductor layer in the channel width direction is substantially triangular or substantially trapezoidal. The effective channel width is shorter than that for a rectangular cross section.

    Semiconductor device
    13.
    发明授权
    Semiconductor device 有权

    公开(公告)号：US09614100B2

    公开(公告)日：2017-04-04

    申请号：US14617308

    申请日：2015-02-09

    Applicant: Semiconductor Energy Laboratory Co., Ltd.

    Inventor： Shunpei Yamazaki ,  Daisuke Matsubayashi ,  Yutaka Okazaki

    IPC: H01L29/786 ,  H01L27/088 ,  H01L29/78

    CPC classification number: H01L29/7869 ,  H01L29/785 ,  H01L29/78609 ,  H01L29/78696

    Abstract: The semiconductor device includes a transistor including an oxide semiconductor film having a channel formation region, a gate insulating film, and a gate electrode layer. In the transistor, the channel length is small (5 nm or more and less than 60 nm, preferably 10 nm or more and 40 nm or less), and the thickness of the gate insulating film is large (equivalent oxide thickness which is obtained by converting into a thickness of silicon oxide containing nitrogen is 5 nm or more and 50 nm or less, preferably 10 nm or more and 40 nm or less). Alternatively, the channel length is small (5 nm or more and less than 60 nm, preferably 10 nm or more and 40 nm or less), and the resistivity of the source region and the drain region is 1.9×10−5 Ω·m or more and 4.8×10−3 Ω·m or less.

    Semiconductor device
    14.
    发明授权
    Semiconductor device 有权
    半导体器件

    公开(公告)号：US09412877B2

    公开(公告)日：2016-08-09

    申请号：US14176472

    申请日：2014-02-10

    Applicant: Semiconductor Energy Laboratory Co., Ltd.

    Inventor： Tetsuhiro Tanaka ,  Yasumasa Yamane ,  Hideomi Suzawa ,  Daisuke Matsubayashi ,  Shunpei Yamazaki

    IPC: H01L27/14 ,  H01L29/786

    CPC classification number: H01L29/78696 ,  H01L29/7869

    Abstract: A transistor or the like having excellent electrical characteristics is provided. A semiconductor device includes a gate electrode; a gate insulating film in contact with the gate electrode; and a multilayer film which is in contact with the gate insulating film and includes a first oxide semiconductor layer, a second oxide semiconductor layer, and a third oxide semiconductor layer in the order from a side farthest from the gate insulating film. The first oxide semiconductor layer, the second oxide semiconductor layer, and the third oxide semiconductor layer each contain indium, an element M (aluminum, gallium, yttrium, or tin), and zinc. The first oxide semiconductor layer has a thickness greater than or equal to 20 nm and less than or equal to 200 nm. The third oxide semiconductor layer has a thickness greater than or equal to 0.3 nm and less than 10 nm.

    Abstract translation: 提供具有优异电特性的晶体管等。 半导体器件包括栅电极; 与栅电极接触的栅极绝缘膜; 以及与所述栅极绝缘膜接触并且从距离所述栅极绝缘膜最远的一侧依次包括第一氧化物半导体层，第二氧化物半导体层和第三氧化物半导体层的多层膜。 第一氧化物半导体层，第二氧化物半导体层和第三氧化物半导体层各自含有铟，元素M（铝，镓，钇或锡）和锌。 第一氧化物半导体层具有大于或等于20nm且小于或等于200nm的厚度。 第三氧化物半导体层的厚度大于或等于0.3nm且小于10nm。

    Semiconductor device and method for manufacturing the same
    16.
    发明授权
    Semiconductor device and method for manufacturing the same 有权
    半导体装置及其制造方法

    公开(公告)号：US09324876B2

    公开(公告)日：2016-04-26

    申请号：US14474533

    申请日：2014-09-02

    Applicant: Semiconductor Energy Laboratory Co., Ltd.

    Inventor： Yoshiyuki Kobayashi ,  Daisuke Matsubayashi

    IPC: H01L31/06 ,  H01L29/786 ,  H01L29/417

    CPC classification number: H01L29/7869 ,  H01L29/41733 ,  H01L29/78696

    Abstract: A semiconductor device includes a first oxide semiconductor film over an insulating surface; a second oxide semiconductor film over the first oxide semiconductor film; a source electrode and a drain electrode in contact with side surfaces of the first oxide semiconductor film, side surfaces of the second oxide semiconductor film, and the top surface of the second oxide semiconductor film; a third oxide semiconductor film over the second oxide semiconductor film, the source electrode, and the drain electrode; a gate insulating film over the third oxide semiconductor film; and a gate electrode in contact with the top surface of the gate insulating film. A length obtained by subtracting a channel length between the source electrode and the drain electrode from a length of the second oxide semiconductor film in the channel length direction is 0.2 times to 2.0 times as long as the channel length.

    Abstract translation: 半导体器件包括绝缘表面上的第一氧化物半导体膜; 第一氧化物半导体膜上的第二氧化物半导体膜; 与第一氧化物半导体膜的侧表面，第二氧化物半导体膜的侧表面和第二氧化物半导体膜的顶表面接触的源电极和漏电极; 第二氧化物半导体膜上的第三氧化物半导体膜，源电极和漏电极; 第三氧化物半导体膜上的栅极绝缘膜; 以及与栅极绝缘膜的顶表面接触的栅电极。 通过从沟道长度方向上的第二氧化物半导体膜的长度减去源电极和漏电极之间的沟道长度而获得的长度是沟道长度的0.2倍至2.0倍。

    Semiconductor device
    17.
    发明授权
    Semiconductor device 有权
    半导体器件

    公开(公告)号：US09312392B2

    公开(公告)日：2016-04-12

    申请号：US14272867

    申请日：2014-05-08

    Applicant: Semiconductor Energy Laboratory Co., Ltd.

    Inventor： Shunpei Yamazaki ,  Masahiko Hayakawa ,  Daisuke Matsubayashi

    IPC: H01L29/10 ,  H01L29/12 ,  H01L29/786

    CPC classification number: H01L29/7869 ,  H01L29/78648 ,  H01L29/78696

    Abstract: A semiconductor device includes a dual-gate transistor in which an oxide semiconductor film is provided between a first gate electrode and a second gate electrode. In the channel width direction of the transistor, a side surface of each of the first and second gate electrodes is on the outer side of a side surface of the oxide semiconductor film. The first or second gate electrode faces the side surface of the oxide semiconductor film with the gate insulating film provided between the first or second gate electrode and the oxide semiconductor film.

    Abstract translation: 半导体器件包括双栅极晶体管，其中在第一栅电极和第二栅电极之间设置氧化物半导体膜。 在晶体管的沟道宽度方向上，第一和第二栅电极的侧面位于氧化物半导体膜的侧面的外侧。 第一或第二栅极电极面对氧化物半导体膜的侧表面，其中栅极绝缘膜设置在第一或第二栅电极和氧化物半导体膜之间。

    Memory device
    18.
    发明授权
    Memory device 有权
    内存设备

    公开(公告)号：US09105313B2

    公开(公告)日：2015-08-11

    申请号：US14587593

    申请日：2014-12-31

    Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

    Inventor： Daisuke Matsubayashi

    IPC: G11C5/06 ,  G11C7/18 ,  G11C5/02 ,  G09B19/00

    CPC classification number: G11C5/06 ,  G09B19/0038 ,  G11C5/025 ,  G11C7/18 ,  G11C15/04 ,  G11C15/046

    Abstract: A memory cell includes a first transistor controlling writing of the first date by being in an on state, and holding of the first data by being in an off state, a second transistor in which a potential of one of a source and a drain is a potential of the second data and a potential of a gate is a potential of the first data, and a third transistor which has a conductivity type opposite to that of the second transistor, which has one of a source and a drain electrically connected to the other of the source and the drain of the second transistor, and in which a potential of a gate is a potential of the first data.

    Abstract translation: 存储单元包括第一晶体管，其控制第一日期的写入处于导通状态，并且通过处于截止状态来保持第一数据;第二晶体管，其源极和漏极之一的电位为 第二数据的电位和栅极的电位是第一数据的电位，并且具有与第二晶体管的导电类型相反的导电类型的第三晶体管，其具有与另一个电连接的源极和漏极之一 的第二晶体管的源极和漏极，并且其中栅极的电位是第一数据的电位。

    MEMORY DEVICE
    20.
    发明申请
    MEMORY DEVICE 有权
    内存设备

    公开(公告)号：US20150117082A1

    公开(公告)日：2015-04-30

    申请号：US14587593

    申请日：2014-12-31

    Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

    Inventor： Daisuke Matsubayashi

    IPC: G11C5/06

    CPC classification number: G11C5/06 ,  G09B19/0038 ,  G11C5/025 ,  G11C7/18 ,  G11C15/04 ,  G11C15/046

    Abstract: A memory cell includes a first transistor controlling writing of the first date by being in an on state, and holding of the first data by being in an off state, a second transistor in which a potential of one of a source and a drain is a potential of the second data and a potential of a gate is a potential of the first data, and a third transistor which has a conductivity type opposite to that of the second transistor, which has one of a source and a drain electrically connected to the other of the source and the drain of the second transistor, and in which a potential of a gate is a potential of the first data.

    Abstract translation: 存储单元包括第一晶体管，其控制第一日期的写入处于导通状态，并且通过处于截止状态来保持第一数据;第二晶体管，其源极和漏极之一的电位为 第二数据的电位和栅极的电位是第一数据的电位，并且具有与第二晶体管的导电类型相反的导电类型的第三晶体管，其具有与另一个电连接的源极和漏极之一 的第二晶体管的源极和漏极，并且其中栅极的电位是第一数据的电位。

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