公开(公告)号：US11101299B2

公开(公告)日：2021-08-24

申请号：US16107536

申请日：2018-08-21

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

Inventor： Shunpei Yamazaki ,  Satoshi Murakami ,  Masahiko Hayakawa ,  Kiyoshi Kato ,  Mitsuaki Osame

IPC: H01L27/12 ,  H01L33/52 ,  G02F1/1362 ,  H01L27/32 ,  H01L51/52 ,  H01L27/13

Abstract: It is an object of the present invention to provide a semiconductor display device having an interlayer insulating film which can obtain planarity of a surface while controlling film formation time, can control treatment time of heating treatment with an object of removing moisture, and can prevent moisture in the interlayer insulating film from being discharged to a film or an electrode adjacent to the interlayer insulating film. An inorganic insulating film containing nitrogen, which is less likely to transmit moisture compared with an organic resin, is formed so as to cover a TFT. Next, an organic resin film containing photosensitive acrylic resin is applied to the organic insulting film, and the organic resin film is partially exposed to light to be opened. Thereafter, an inorganic insulting film containing nitrogen, which is less likely to transmit moisture compared with an organic resin, is fanned so as to cover the opened organic resin film. Then, in the opening part of the organic resin film, a gate insulating film and the two layer inorganic insulating film containing nitrogen are opened partially by etching to expose an active layer of the TFT.

公开(公告)号：US10860080B2

公开(公告)日：2020-12-08

申请号：US16476642

申请日：2018-01-09

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shuhei Maeda ,  Shuhei Nagatsuka ,  Tatsuya Onuki ,  Kiyoshi Kato

IPC: G11C11/409 ,  G06F1/3234 ,  G11C5/14 ,  G11C14/00 ,  G11C16/30

Abstract: To reduce the area of a memory cell having a backup function. A storage device includes a cell array, and a row circuit and a column circuit that drive the cell array. The cell array includes a first power supply line, a second power supply line, a word line, a pair of bit lines, a memory cell, and a backup circuit. The cell array is located in a power domain where power gating can be performed. In the power gating sequence of the cell array, data in the memory cell is backed up to the backup circuit. The backup circuit is stacked over a region where the memory cell is formed. A plurality of wiring layers are provided between the backup circuit and the memory cell. The first power supply line, the second power supply line, the word line, and the pair of bit lines are located in different wiring layers.

公开(公告)号：US10714502B2

公开(公告)日：2020-07-14

申请号：US15366418

申请日：2016-12-01

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shunpei Yamazaki ,  Kiyoshi Kato ,  Masayuki Sakakura

IPC: H01L27/12 ,  H01L29/786 ,  H01L27/108

Abstract: A semiconductor device that is suitable for miniaturization and higher density is provided. A semiconductor device includes a first transistor over a semiconductor substrate, a second transistor including an oxide semiconductor over the first transistor, and a capacitor over the second transistor. The capacitor includes a first conductor, a second conductor, and an insulator. The second conductor covers a side surface of the first conductor with an insulator provided therebetween.

公开(公告)号：US10522688B2

公开(公告)日：2019-12-31

申请号：US15380502

申请日：2016-12-15

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

Inventor： Kiyoshi Kato ,  Tomoaki Atsumi ,  Shunpei Yamazaki ,  Haruyuki Baba ,  Shinpei Matsuda

IPC: H01L29/786 ,  H01L27/088 ,  H01L27/12 ,  H01L27/108

Abstract: A semiconductor device capable of holding data for a long time is provided. The semiconductor device includes a first transistor, a second transistor, and a circuit. The first transistor includes a first gate and a second gate. The first transistor includes a first semiconductor in a channel formation region. The first gate and the second gate overlap with each other in a region with the first semiconductor provided therebetween. The second transistor includes a second semiconductor in a channel formation region. A first terminal of the second transistor is electrically connected to a gate of the second transistor and the second gate. A second terminal of the second transistor is electrically connected to the circuit. The circuit has a function of generating a negative potential. The second semiconductor has a wider bandgap than the first semiconductor.

公开(公告)号：US10424671B2

公开(公告)日：2019-09-24

申请号：US15220706

申请日：2016-07-27

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shunpei Yamazaki ,  Kiyoshi Kato ,  Hidekazu Miyairi ,  Akihisa Shimomura ,  Atsushi Hirose

IPC: H01L27/108 ,  H01L29/786 ,  G11C11/24

Abstract: A novel semiconductor device or memory device is provided. Alternatively, a semiconductor device or memory device in which storage capacity per unit area is large is provided. The semiconductor device includes a sense amplifier provided to a semiconductor substrate and a memory cell provided over the sense amplifier. The sense amplifier includes a first transistor. The memory cell includes a capacitor over the semiconductor substrate, a second transistor provided over the capacitor, a conductor, and a groove portion. The capacitor includes a first electrode and a second electrode. The first electrode is formed along the groove portion. The second electrode has a region facing the first electrode in the groove portion. The second transistor includes an oxide semiconductor. One of a source and a drain of the second transistor is electrically connected to the second electrode through the conductor.

公开(公告)号：US10367005B2

公开(公告)日：2019-07-30

申请号：US15966231

申请日：2018-04-30

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shunpei Yamazaki ,  Yuta Endo ,  Kiyoshi Kato ,  Satoru Okamoto

IPC: H01L27/12 ,  H01L21/02 ,  H01L21/768 ,  H01L23/528 ,  H01L23/532 ,  H01L27/105 ,  H01L29/24 ,  H01L29/66 ,  H01L29/786 ,  H01L21/8258 ,  H01L27/06 ,  H01L21/3105 ,  H01L21/3115 ,  H01L27/088 ,  H01L27/092

Abstract: A highly reliable semiconductor device suitable for miniaturization and high integration is provided. The semiconductor device includes a first insulator; a transistor over the first insulator; a second insulator over the transistor; a first conductor embedded in an opening in the second insulator; a barrier layer over the first conductor; a third insulator over the second insulator and over the barrier layer; and a second conductor over the third insulator. The first insulator, the third insulator, and the barrier layer have a barrier property against oxygen and hydrogen. The second insulator includes an excess-oxygen region. The transistor includes an oxide semiconductor. The barrier layer, the third insulator, and the second conductor function as a capacitor.

公开(公告)号：US10250247B2

公开(公告)日：2019-04-02

申请号：US15427815

申请日：2017-02-08

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Kiyoshi Kato ,  Yutaka Shionoiri ,  Tomoaki Atsumi ,  Takanori Matsuzaki

IPC: H03K5/24 ,  G11C5/14 ,  H01L21/78 ,  H01L27/00 ,  H01L49/02 ,  H01L23/498 ,  H01L27/108 ,  H01L27/146

Abstract: Provided is a semiconductor device that can directly compare two negative potentials. The semiconductor device includes a first to a third transistor and a load and is configured to compare a first negative potential and a second negative potential. The first negative potential and the second negative potential are input to a gate of the first transistor and a gate of the second transistor, respectively. Each drain of the first transistor and the second transistor is electrically connected to the load. The third transistor serves as a current source. The first transistor and the second transistor each include a backgate. A positive potential is input to the backgates.

公开(公告)号：US10217736B2

公开(公告)日：2019-02-26

申请号：US14492412

申请日：2014-09-22

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

Inventor： Kiyoshi Kato ,  Hidekazu Miyairi ,  Shuhei Nagatsuka

IPC: H01L27/06 ,  H01L27/12 ,  H01L27/108 ,  H01L27/1156

Abstract: A highly integrated semiconductor device including a transistor and a capacitor which occupies a small area for the required on-state current and required capacitance is provided. The semiconductor device includes a semiconductor, first and second conductive films each in contact with top and side surfaces of the semiconductor, a first insulating film in contact with the top and side surfaces of the semiconductor, a third conductive film facing the top and side surfaces of the semiconductor with the first insulating film therebetween, a second insulating film which is in contact with the first conductive film and comprises an opening, a fourth conductive film in contact with the opening, a third insulating film facing the opening with the fourth conductive film therebetween, and a fifth conductive film facing the fourth conductive film with the third insulating film therebetween.

公开(公告)号：US10128247B2

公开(公告)日：2018-11-13

申请号：US15477144

申请日：2017-04-03

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shunpei Yamazaki ,  Jun Koyama ,  Kiyoshi Kato

IPC: H01L27/108 ,  H01L27/105 ,  G11C11/24 ,  H01L27/1156 ,  H01L27/12 ,  H01L49/02

Abstract: A semiconductor device including a non-volatile memory cell including a writing transistor which includes an oxide semiconductor, a reading transistor which includes a semiconductor material different from that of the writing transistor, and a capacitor is provided. Data is written or rewritten to the memory cell by turning on the writing transistor and supplying a potential to a node where a source electrode (or a drain electrode) of the writing transistor, one electrode of the capacitor, and a gate electrode of the reading transistor are electrically connected to each other, and then turning off the writing transistor so that the predetermined amount of charge is held in the node. Further, when a transistor whose threshold voltage is controlled and set to a positive voltage is used as the reading transistor, a reading potential is a positive potential.

公开(公告)号：US10121904B2

公开(公告)日：2018-11-06

申请号：US15678180

申请日：2017-08-16

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Kiyoshi Kato ,  Jun Koyama

IPC: H04B1/06 ,  H04B7/00 ,  H04B1/28 ,  H04M1/00 ,  H01L29/786 ,  H01L27/06 ,  H01L27/12 ,  H04B1/40 ,  G06K19/077 ,  H01L29/10 ,  H01L23/66

Abstract: An object is to achieve low power consumption and a long lifetime of a semiconductor device having a wireless communication function. The object can be achieved in such a manner that a battery serving as a power supply source and a specific circuit are electrically connected to each other through a transistor in which a channel formation region is formed using an oxide semiconductor. The hydrogen concentration of the oxide semiconductor is lower than or equal to 5×1019 (atoms/cm3). Therefore, leakage current of the transistor can be reduced. As a result, power consumption of the semiconductor device in a standby state can be reduced. Further, the semiconductor device can have a long lifetime.